Abstract:
A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.
Abstract:
The present invention provides a method of recycling a spent flue gas denitration catalyst and a method of determining a washing time of the spent flue gas denitration catalyst. The method of recycling the spent flue gas denitration catalyst includes physically removing solids deposited in the spent flue gas denitration catalyst, removing poisoning substances deposited in the spent flue gas denitration catalyst by washing the spent flue gas denitration catalyst with a washing liquid for a washing time determined by measuring the hydrogen ion concentration of the washing liquid and drying the resulting spent flue gas denitration catalyst.
Abstract:
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
Abstract:
A variable phase shifter is provided. In the variable phase shifter, a fixed substrate, which is a dielectric substrate, is fixedly mounted in a housing and has at least one arc-shaped microstrip line on one surface thereof. A rotation substrate, which is a dielectric substrate, is rotatably mounted in the housing, in contact with the other surface of the fixed substrate and has a slot line on the contact surface thereof. Microstrip-slot line coupling takes place between the microstrip line and the slot line even during rotation. Both ends of the microstrip line are connected to an output port of the variable phase shifter and the slot line is electrically connected to an input port of the variable phase shifter, for receiving an input signal.
Abstract:
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.
Abstract:
The present invention relates to a segregation reducing agent consisting of curdlan and alkaline materials and a hydraulic composition containing the segragation reducing agent, particularly, the present invention relates to the segregation reducing agent prepared by alkalifying a curdlan-producing fermentation broth per se or a curdlan powder with an alkaline material, and also relates to hydraulic compositions, concrete and mortar, comprising the segregation educing agent. This segregation reducing agent can provide a great segregation reduction effect for hydraulic compositions even at its small amount as well as guarantee the strength, filling ability and fluidity.
Abstract:
A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.
Abstract:
A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.
Abstract:
A variable phase shifter is provided. In the variable phase shifter, a fixed substrate, which is a dielectric substrate, is fixedly mounted in a housing and has at least one arc-shaped microstrip line on one surface thereof. A rotation substrate, which is a dielectric substrate, is rotatably mounted in the housing, in contact with the other surface of the fixed substrate and has a slot line on the contact surface thereof. Microstrip-slot line coupling takes place between the microstrip line and the slot line even during rotation. Both ends of the microstrip line are connected to an output port of the variable phase shifter and the slot line is electrically connected to an input port of the variable phase shifter, for receiving an input signal.
Abstract:
A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.