公开(公告)号：US09471522B2

公开(公告)日：2016-10-18

申请号：US14096574

申请日：2013-12-04

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/287 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/4022

Abstract: According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.

Abstract translation: 根据本发明的实施例，公开了用于虚拟信道管理和总线复用的方法，计算机系统和装置。 该方法可以包括经由总线建立从第一设备到第二设备的虚拟通道，总线具有第一总线容量和第二总线容量，第二总线容量具有比第一总线容量更大的容量，确定存储 发出第一总线容量的命令，确定第一总线容量是否可用，并且如果第一总线容量不可用，则分配第二总线容量并且响应于存储命令将第二总线容量标记为不可用。

公开(公告)号：US20240119000A1

公开(公告)日：2024-04-11

申请号：US17962829

申请日：2022-10-10

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Matthias Klein ,  Sascha Junghans ,  Kevin Lopes

IPC: G06F12/0802 ,  G06F13/16

CPC classification number: G06F12/0802 ,  G06F13/1668 ,  G06F2212/621

Abstract: A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.

公开(公告)号：US11249776B2

公开(公告)日：2022-02-15

申请号：US16789519

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marco Kraemer ,  Christoph Raisch ,  Bernd Nerz ,  Donald William Schmidt ,  Matthias Klein ,  Sascha Junghans ,  Peter Dana Driever

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

公开(公告)号：US11023398B2

公开(公告)日：2021-06-01

申请号：US16789567

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Christoph Raisch ,  Marco Kraemer ,  Donald William Schmidt ,  Bernd Nerz ,  Sascha Junghans ,  Peter Dana Driever

IPC: G06F9/48 ,  G06F13/24 ,  G06F12/1009 ,  G06F9/455

Abstract: An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

公开(公告)号：US20200264910A1

公开(公告)日：2020-08-20

申请号：US16789519

申请日：2020-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marco Kraemer ,  Christoph Raisch ,  Bernd Nerz ,  Donald William Schmidt ,  Matthias Klein ,  Sascha Junghans ,  Peter Dana Driever

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

公开(公告)号：US10529396B2

公开(公告)日：2020-01-07

申请号：US15629923

申请日：2017-06-22

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Sascha Junghans ,  Matthias Klein ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Chad G. Wilson

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C8/06

Abstract: A system and method to transfer an ordered partial store of data from a controller to a memory subsystem receives the ordered partial store of data into a buffer of the controller. The method also includes issuing a preinstall command to the memory subsystem, wherein the preinstall command indicates that data from a number of addresses of memory corresponding with a target memory location be obtained in local memory of the memory subsystem along with ownership of the data for subsequent use. A query command is issued to the memory subsystem. The query command requests an indication from the memory subsystem that the memory subsystem is ready to receive and correctly serialize the ordered partial store of data. The ordered partial store of data is transferred from the controller to the memory subsystem.

公开(公告)号：US10423546B2

公开(公告)日：2019-09-24

申请号：US15806407

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Girish G. Kurup

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/28 ,  G06F13/42

Abstract: A method for coupling transactions with a configurable ordering controller in a computer system. The method comprises sending, by a coupling device, first data packets with an unordered attribute being set to an ordering controller. The method further comprises sending, by the coupling device, second data packets with requested ordering to the ordering controller, back-to-back after the first data packets, without waiting until all of the first data packets are completed. The method further comprises sending, by the ordering controller, the first data packets to a memory subsystem in a relaxed ordering mode, wherein the ordering controller sends the first data packets to the memory subsystem in an arbitrary order, and wherein the ordering controller sends the second data packets to the memory subsystem after sending all of the first data packets to the memory subsystem.

公开(公告)号：US20180365180A1

公开(公告)日：2018-12-20

申请号：US15623429

申请日：2017-06-15

Applicant: International Business Machines Corporation

Inventor： David F. Craddock ,  Sascha Junghans ,  Matthias Klein ,  Eric N. Lais

IPC: G06F13/28 ,  G06F12/1027 ,  G06F13/42 ,  G06F12/1009 ,  G06F12/1081

CPC classification number: G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1081 ,  G06F13/4282

Abstract: Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

公开(公告)号：US09864579B2

公开(公告)日：2018-01-09

申请号：US15408747

申请日：2017-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sascha Junghans ,  Matthias Klein ,  Thomas Schlipf

IPC: G06F3/00 ,  G06F5/00 ,  G06F7/544 ,  G06F7/57 ,  G06F17/30

CPC classification number: G06F7/544 ,  G06F1/0328 ,  G06F1/1615 ,  G06F7/57 ,  G06F9/3838 ,  G06F12/1018 ,  G06F17/30109 ,  G06F17/30949 ,  G06F2212/401

Abstract: Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

公开(公告)号：US09767048B2

公开(公告)日：2017-09-19

申请号：US14862221

申请日：2015-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Norbert Hagspiel ,  Sascha Junghans ,  Matthias Klein ,  Joerg Walter

IPC: G06F13/10 ,  G06F13/20 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/20 ,  G06F13/4068

Abstract: A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.