公开(公告)号：US09875189B2

公开(公告)日：2018-01-23

申请号：US14738037

申请日：2015-06-12

申请人： INTEL CORPORATION

发明人： Krystof C. Zmudzinski ,  Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Ilya Alexandrovich ,  Ittai Anati ,  Wesley H. Smith ,  Michael Goldsmith

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/14 ,  G06F9/455 ,  G06F12/1045

CPC分类号： G06F12/1009 ,  G06F9/455 ,  G06F9/45558 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/1441 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/657 ,  G06F2212/684

摘要： A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

公开(公告)号：US09766889B2

公开(公告)日：2017-09-19

申请号：US15074573

申请日：2016-03-18

申请人： Intel Corporation

发明人： Rebekah Leslie-Hurd ,  Carlos V. Rozas ,  Vincent R. Scarlata ,  Simon P. Johnson ,  Uday R. Savagaonkar ,  Barry E. Huntley ,  Vedvyas Shanbhogue ,  Ittai Anati ,  Francis X. Mckeen ,  Michael A. Goldsmith ,  Ilya Alexandrovich ,  Alex Berenzon ,  Wesley H. Smith ,  Gilbert Neiger

IPC分类号： G06F12/00 ,  G06F9/30 ,  G06F12/0875 ,  G06F9/44 ,  G06F12/084 ,  G06F12/14

CPC分类号： G06F9/3004 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/44 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1483 ,  G06F2212/452

摘要： Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.

公开(公告)号：US09710393B2

公开(公告)日：2017-07-18

申请号：US14750982

申请日：2015-06-25

申请人： Intel Corporation

发明人： Michael Lemay ,  David M. Durham ,  Andrew V. Anderson ,  Gilbert Neiger ,  Ravi L. Sahita

IPC分类号： G06F12/00 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/14 ,  G06F9/455 ,  G06F21/00

CPC分类号： G06F12/1009 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/1027 ,  G06F12/1483 ,  G06F21/00 ,  G06F21/53 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1024 ,  G06F2212/1052 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2221/2141

摘要： Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.

公开(公告)号：US20170109192A1

公开(公告)日：2017-04-20

申请号：US15391576

申请日：2016-12-27

申请人： Intel Corporation

发明人： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC分类号： G06F9/455 ,  G06F9/48

CPC分类号： G06F9/45558 ,  G06F9/30076 ,  G06F9/45533 ,  G06F9/4555 ,  G06F9/4812 ,  G06F11/07 ,  G06F2009/45583

摘要： Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US09442868B2

公开(公告)日：2016-09-13

申请号：US14565718

申请日：2014-12-10

申请人： Intel Corporation

发明人： Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard A. Uhlig ,  Udo Steinberg ,  Sebastian Schoenberg ,  Sridhar Muthrasanallur ,  Steven M. Bennett ,  Andrew V. Anderson ,  Erik C. Cota-Robles

IPC分类号： G06F9/445 ,  G06F9/46 ,  G06F13/24 ,  G06F13/26 ,  G06F3/00 ,  G06F13/00 ,  G06F9/455 ,  G06F9/48

CPC分类号： G06F13/24 ,  G06F9/45533 ,  G06F9/4812

摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.

公开(公告)号：US20160188504A1

公开(公告)日：2016-06-30

申请号：US14800419

申请日：2015-07-15

申请人： Intel Corporation

发明人： Rajesh Sankaran Madukkarumukumana ,  Gilbert Neiger ,  Ohad Falik ,  Sridhar Muthrasanallur ,  Gideon Gerzon

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

公开(公告)号：US09372807B2

公开(公告)日：2016-06-21

申请号：US14867027

申请日：2015-09-28

申请人： Intel Corporation

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F9/455 ,  G06F12/08

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09372806B2

公开(公告)日：2016-06-21

申请号：US14867024

申请日：2015-09-28

申请人： Intel Corporation

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F9/455 ,  G06F12/08

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09330021B2

公开(公告)日：2016-05-03

申请号：US14867020

申请日：2015-09-28

申请人： Intel Corporation

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F9/455 ,  G06F12/08

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09244712B2

公开(公告)日：2016-01-26

申请号：US14060947

申请日：2013-10-23

申请人： Intel Corporation

发明人： Erik C. Cola-Robles ,  Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F11/34

CPC分类号： G06F9/45533 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/46 ,  G06F9/461 ,  G06F9/462 ,  G06F9/468 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F2009/45591 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.

摘要翻译： 公开了用于虚拟化性能计数器的装置，方法和系统的实施例。 在一个实施例中，装置包括计数器，计数器使能存储位置，计数器使能逻辑和虚拟机器控制逻辑。 计数器使能存储位置是存储计数器使能指示符。 计数器使能逻辑是基于计数器使能指示器启用计数器。 虚拟机控制逻辑是将设备的控制传送给客人。 虚拟机控制逻辑包括客户端状态负载逻辑，以使来自虚拟机控制结构的客户值被加载到计数器使能存储位置中，并将该设备的控制转移给客户端。