公开(公告)号：US20070127303A1

公开(公告)日：2007-06-07

申请号：US11626256

申请日：2007-01-23

申请人： Mirmajid Seyyedy ,  Mark Tuttle ,  Glen Hush

发明人： Mirmajid Seyyedy ,  Mark Tuttle ,  Glen Hush

IPC分类号： G11C17/18

CPC分类号： H01L27/222 ,  G11C11/005 ,  G11C11/15 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least some of the MRAM cells are designed to function as antifuse devices whereby the application of a selected electrical potential can short the antifuse device to thereby affect the functionality of the MRAM device.

摘要翻译： 具有由固定磁性层形成的多个MRAM单元的MRAM器件，第二软磁性层和介于该固定磁性层与软磁性层之间的电介质层。 MRAM单元都是同时形成的，并且至少一些MRAM单元被设计为用作反熔丝器件，由此施加所选择的电位可以使反熔丝器件短路从而影响MRAM器件的功能。

公开(公告)号：US06751117B2

公开(公告)日：2004-06-15

申请号：US10435029

申请日：2003-05-12

申请人： Tom W. Voshell ,  Mirmajid Seyyedy

发明人： Tom W. Voshell ,  Mirmajid Seyyedy

IPC分类号： G11C1100

CPC分类号： G11C11/16

摘要： A method and apparatus for selecting a rowline in a MRAM device. A rowline select circuit is provided on a first side of each rowline and connects the rowline to ground when a memory cell in the rowline is being written to and to a voltage source when a memory cell in the rowline is being read. A rowline stack select circuit is provided on the second side of each rowline and is connected to one rowline on each plane of memory. When a memory cell is being accessed, the rowline containing that memory cell as well as each other rowline connected to the same rowline stack select circuit are connected to a current source.

摘要翻译： 一种用于在MRAM设备中选择行线的方法和设备。 当行行中的存储单元正被读取时，行列线的第一侧上提供行线选择电路，并且当行行中的存储单元正在被读取时，将行线连接到地， 行排线选择电路设置在每行行的第二侧，并连接到存储器的每个平面上的一行。 当访问存储单元时，包含该存储单元的行线以及连接到相同行线栈选择电路的每条行线连接到当前源。

公开(公告)号：US06424584B1

公开(公告)日：2002-07-23

申请号：US09293353

申请日：1999-04-16

申请人： Mirmajid Seyyedy

发明人： Mirmajid Seyyedy

IPC分类号： G11C700

CPC分类号： G11C29/787 ,  G11C17/18

摘要： A detector circuit for detecting a digital word matching a bit pattern programmed by fusible devices. The detector circuit includes decoder circuits coupled to first and second sense nodes, and a reference node, and further includes an evaluation circuit also coupled to the first and second sense nodes. The evaluation circuit senses the voltage of both sense nodes and produces a match signal according to these voltages. The voltage of the first and second sense nodes are determined by the programmed status of the decoder circuit and whether a matching bit is detected. The decoder circuit includes a fusible device, such as an antifuse, and a switch having a control terminal coupled to receive one bit of the digital word. An enable circuit may also be coupled to the detector circuit to either enable or disable operation of the detector circuit based on whether the enable circuit has been programmed.

摘要翻译： 一种检测电路，用于检测与可熔设备编程的位模式匹配的数字字。 检测器电路包括耦合到第一和第二感测节点的解码器电路和参考节点，并且还包括还耦合到第一和第二感测节点的评估电路。 评估电路感测两个感测节点的电压，并根据这些电压产生匹配信号。 第一和第二感测节点的电压由解码器电路的编程状态以及是否检测到匹配位来确定。 解码器电路包括诸如反熔丝的可熔设备，以及具有耦合以接收数字字的一位的控制端的开关。 使能电路还可以耦合到检测器电路，以基于使能电路是否被编程来启用或禁用检测器电路的操作。

公开(公告)号：US06320816B2

公开(公告)日：2001-11-20

申请号：US09813185

申请日：2001-03-20

申请人： Mirmajid Seyyedy ,  Jeffrey P. Wright

发明人： Mirmajid Seyyedy ,  Jeffrey P. Wright

IPC分类号： G11C800

CPC分类号： G11C8/10 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4087

摘要： A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

摘要翻译： 描述了使用独特的列选择电路的同步存储器件。 存储器件管线地址解码和列选择操作以增加时钟频率。 列选择电路包括锁存器和耦合电路。 锁存器用于锁存列选择电路。 耦合电路将列选择信号与存储单元列隔离，直到提供使能信号。 地址解码可以与使能信号组合以减少存储单元组所需的锁存电路的总数。

公开(公告)号：US06201740B1

公开(公告)日：2001-03-13

申请号：US09291536

申请日：1999-04-14

申请人： Mirmajid Seyyedy ,  Paul S. Zagar

发明人： Mirmajid Seyyedy ,  Paul S. Zagar

IPC分类号： G11C700

CPC分类号： G11C7/18 ,  G11C7/1072

摘要： A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.

摘要翻译： 描述了使用多路复用的锁存结构和全局位线的动态存储器。 多路复用架构允许存储器在计算机处理系统中作为同步流水线缓存存储器操作。 全局位线与存储器阵列位线并行制造，并且数据输入/输出连接分布在存储器周围以增加速度。 提供了多路复用的锁存电路，其中包含用于数据读取和写入操作的单独的数据路径。

公开(公告)号：US6004825A

公开(公告)日：1999-12-21

申请号：US27686

申请日：1998-02-23

申请人： Mirmajid Seyyedy

发明人： Mirmajid Seyyedy

IPC分类号： G11C11/22 ,  H01L27/115 ,  H01L21/00

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A three dimensional ferroelectric memory device formed on a semiconductor substrate has insulative material formed between rows of conductors to reduce cross talk between the conductors. Access circuitry or other circuitry is formed beneath the three dimensional structure. Continuous conductors, or staggered vias provide for connection to conductors forming the memory cells. An access circuit is provided which eliminates the need for an access transistor for each memory cell by using a memory cell with a reference cell in combination with sensing circuitry. Read cycles are followed by write cycles and an equilibrate cycle to reverse the effects of destructive reads on the memory cells. Side by side memory structures provide the ability to access using either a folded or open bit line circuit.

摘要翻译： 形成在半导体基板上的三维铁电存储器件具有形成在导体列之间的绝缘材料，以减少导体之间的串扰。 在三维结构之下形成访问电路或其他电路。 连续导体或交错通孔提供连接到形成存储器单元的导体。 提供了一种访问电路，其通过使用具有与感测电路组合的参考单元的存储单元来消除对每个存储单元的访问晶体管的需要。 读周期之后是写周期和平衡周期，以反转破坏性读取对存储器单元的影响。 并行记忆结构提供使用折叠或开放位线电路访问的能力。

公开(公告)号：US5905672A

公开(公告)日：1999-05-18

申请号：US30706

申请日：1998-02-25

申请人： Mirmajid Seyyedy

发明人： Mirmajid Seyyedy

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A random access memory circuit is described which uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using reference cells to generate a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. In using two ferroelectric reference cells in which one contains a logical 0 polarization, and the other contains a logical 1 polarization, a single-ended reference voltage can be generated on a reference bit line. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference bit line using the sense amplifier. The content of the memory cell being read and the content of the reference cells can be rewritten on the same clock cycles to save on access time.

摘要翻译： 描述了使用单个铁电存储器单元来存储数据的随机存取存储器电路。 可以使用参考单元选择性地读取铁电存储单元，以产生与使用多路复用读出放大器代表存储在存储单元上的数据的电压进行比较的参考电压。 在使用其中包含逻辑0极化的两个铁电参考单元，另一个包含逻辑1极化时，可以在参考位线上生成单端参考电压。 然后可以通过使用读出放大器将其对应位线上的电压与参考位线进行比较来读取铁电存储器单元。 正在读取的存储单元的内容和参考单元的内容可以在相同的时钟周期上重写以节省存取时间。

公开(公告)号：US5726931A

公开(公告)日：1998-03-10

申请号：US804182

申请日：1997-02-20

申请人： Paul S. Zagar ,  Mirmajid Seyyedy

发明人： Paul S. Zagar ,  Mirmajid Seyyedy

IPC分类号： G11C11/401 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C11/24 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/18 ,  G11C11/4097 ,  G11C11/4099 ,  G11C7/14

摘要： A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical characteristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.

公开(公告)号：US20100044668A1

公开(公告)日：2010-02-25

申请号：US12614314

申请日：2009-11-06

申请人： Mirmajid Seyyedy ,  Glen Hush

发明人： Mirmajid Seyyedy ,  Glen Hush

IPC分类号： H01L47/00 ,  H01L21/00 ,  H01L21/4763 ,  H01L29/82

CPC分类号： G11C11/1653 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2213/71

摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

摘要翻译： 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取在“Z”轴方向上布置的多个MRAM阵列层中可以彼此垂直堆叠的列的段中的多个MRAM单元。

公开(公告)号：US06831361B2

公开(公告)日：2004-12-14

申请号：US09911116

申请日：2001-07-23

申请人： Mirmajid Seyyedy

发明人： Mirmajid Seyyedy

IPC分类号： H01L2348

CPC分类号： H01L23/3121 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49811 ,  H01L2224/73203

摘要： An apparatus for connecting one substrate, such as a flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate is disclosed. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

摘要翻译： 公开了一种用于将诸如倒装芯片型半导体管芯的一个基板连接到诸如硅晶片，印刷电路板或其它基板的相对基板的装置。 每个衬底在其相对表面上具有多个导电凸块，其中每个衬底上的导电凸块是另一衬底的镜像。 基板以一种基板上的导电凸块与相对基板上的相应导电凸块形成电接触的方式彼此附接，而无需机械连接。