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公开(公告)号：US10189426B2
公开(公告)日：2019-01-29
申请号：US15411061
申请日：2017-01-20
Inventor： Zhao Zhang , Jian Ouyang , Jing Wang , Peng Wu , Liang Gao , Yupeng Li
IPC: G06F1/08 , G05D1/00 , G06F1/32 , B60L11/18 , B60R16/023
Abstract: The present application discloses a method and apparatus for operating a field-programmable gate array (FPGA) board in a driverless vehicle. The method according to a specific embodiment includes: collecting driving scenario information on a driving scenario of the driverless vehicle; determining, based on the driving scenario information, a speed at which the driverless vehicle executes a computing operation in the driving scenario; comparing the speed with a speed threshold; switching a working mode of the FPGA board in the driverless vehicle executing the computing operation to reduce power consumption of the FPGA board, in response to the speed being lower than the speed threshold. This embodiment implements the adaptive adjustment of the working mode of the FPGA board, thereby reducing the overall power consumption.
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22.发明授权公开(公告)号：US11748108B2
公开(公告)日：2023-09-05
申请号：US17210616
申请日：2021-03-24
Applicant: Beijing Baidu Netcom Science and Technology Co., Ltd. , Kunlunxin Technology (Beijing) Company Limited
Inventor： Yingnan Xu , Jian Ouyang , Xueliang Du , Kang An
CPC classification number: G06F9/3834 , G06F9/30087 , G06F9/3838
Abstract: Example embodiments of the present application provide an instruction executing method and apparatus, an electronic device, and a computer-readable storage medium that may be applied in the field of artificial intelligence. The instruction executing method may include: executing an instruction sequence that includes memory instructions and non-memory instructions, the instructions in the sequence executed starting to be executed in order; determining that execution of a first memory instruction needs to be completed before a second memory instruction starts to be executed, the second memory instruction being a next memory instruction following the first memory instruction in the instruction sequence; and executing non-memory instructions between the first memory instruction and the second memory instruction without executing the second memory instruction, during a cycle of executing the first memory instruction.
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公开(公告)号：US11481994B2
公开(公告)日：2022-10-25
申请号：US16807775
申请日：2020-03-03
Inventor： Zihao Liang , Jian Ouyang
Abstract: Embodiments of the present disclosure provide a method and apparatus for extracting image data in parallel from multiple convolution windows, a device, and a computer-readable storage medium. The method includes: dividing an image into multiple groups of convolution windows, where the multiple groups of convolution windows include a first group of convolution windows and a second group of convolution windows, and each group of convolution windows include multiple convolution windows. The method further includes extracting image data in parallel from multiple convolution windows in the first group of convolution windows by using multiple data processing units, and extracting, after the extraction of image data from the first group of convolution windows is completed, image data from multiple convolution windows in the second group of convolution windows in parallel by using the multiple data processing units.
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公开(公告)号：US11055100B2
公开(公告)日：2021-07-06
申请号：US16502628
申请日：2019-07-03
Inventor： Jian Ouyang
Abstract: Embodiments of the present disclosure relate to a method for processing information, and a processor. The processor includes an arithmetic and logic unit, a bypass unit, a queue unit, a multiplexer, and a register file. The bypass unit includes a data processing subunit; the data processing subunit is configured to acquire at least one valid processing result outputted by the arithmetic and logic unit, determine a processing result from the at least one valid processing result, output the determined processing result to the multiplexer, and output processing results except for the determined processing result of among the at least one valid processing result to the queue unit; and the multiplexer is configured to sequentially output more than one valid processing results to the register file.
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公开(公告)号：US11023391B2
公开(公告)日：2021-06-01
申请号：US16506151
申请日：2019-07-09
Inventor： Peng Wu , Jian Ouyang , Canghai Gu , Wei Qi , Ningyi Xu
Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
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Patent Agency Ranking
公开(公告)号：US10607668B2
公开(公告)日：2020-03-31
申请号：US15281283
申请日：2016-09-30
Inventor： Jian Ouyang , Wei Qi , Yong Wang
Abstract: The present application discloses a data processing method and apparatus. A specific embodiment of the method includes: preprocessing received to-be-processed input data; obtaining a storage address of configuration parameters of the to-be-processed input data based on a result of the preprocessing and a result obtained by linearly fitting an activation function, the configuration parameters being preset according to curve characteristics of the activation function; acquiring the configuration parameters of the to-be-processed input data according to the storage address; and processing the result of the preprocessing of the to-be-processed input data based on the configuration parameters of the to-be-processed input data and a preset circuit structure, to obtain a processing result. This implementation manner implements the processing of the input data to be processed by using the configuration parameter and the preset circuit structure, without the need to use any special circuit for implementing the activation function, thereby simplifying the circuit structure. In addition, this implementation manner can support multiple types of activation functions, thereby improving the flexibility. With such an embodiment, the processing of the input data to be processed can be realized by using the configuration parameters and the preset circuit structure, without the need of using a special circuit to implement the activation function, thereby simplifying the circuit structure, supporting various activation functions, and improving the flexibility.
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公开(公告)号：US20200050557A1
公开(公告)日：2020-02-13
申请号：US16506151
申请日：2019-07-09
Inventor： Peng Wu , Jian Ouyang , Canghai Gu , Wei Qi , Ningyi Xu
Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
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公开(公告)号：US10140251B2
公开(公告)日：2018-11-27
申请号：US15590798
申请日：2017-05-09
Inventor： Ni Zhou , Wei Qi , Yong Wang , Jian Ouyang
Abstract: A processor and a method for executing a matrix multiplication operation on a processor. A specific implementation of the processor includes a data bus and an array processor having k processing units. The data bus is configured to sequentially read n columns of row vectors from an M×N multiplicand matrix and input same to each processing unit in the array processor, read an n×k submatrix from an N×K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation. Each processing unit in the array processor is configured to execute in parallel a vector multiplication operation on the input row and column vectors. Each processing unit includes a Wallace tree multiplier having n multipliers and n−1 adders. This implementation improves the processing efficiency of a matrix multiplication operation.
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公开(公告)号：US09912349B1
公开(公告)日：2018-03-06
申请号：US15628455
申请日：2017-06-20
Inventor： Jian Ouyang , Ni Zhou , Yong Wang , Wei Qi
CPC classification number: H03M7/30 , G06F9/30018 , G06F9/30145 , G06F9/30149 , G06F9/30174 , G06F9/3851 , G06F17/16 , G06N3/02 , G06T15/005 , H03M7/24
Abstract: The present disclosure provides a method and apparatus for processing a floating point number matrix, an apparatus and a computer readable storage medium. In embodiments of the present disclosure, the minimum value of the floating point number model matrix and the maximum value of the floating point number model matrix are obtained according to a floating point number model matrix to be compressed, and then, compression processing is performed for the floating point number model matrix to obtain the fixed point number model matrix according to the bit width, the minimum value of the floating point number model matrix and the maximum value of the floating point number model matrix. The compression processing is performed for the floating point number model matrix of the deep learning model by a fixed point method, to obtain the fixed point number model matrix and reduce the storage space and amount of operation of the deep learning model. Meanwhile, the present disclosure proposes a framework for implementing the apparatus in the deep learning network to maximize the deep learning network precision, that is, a multiplication portion of the matrix uses the apparatus, and operations of other portions such as activation function retain the floating point operation.
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公开(公告)号：US20180052685A1
公开(公告)日：2018-02-22
申请号：US15360245
申请日：2016-11-23
Inventor： Jian Ouyang , Wei Qi , Yong Wang
CPC classification number: G06F9/3016 , G06F9/3001 , G06F9/3004 , G06F9/3802 , G06F9/3824 , G06F9/3877
Abstract: The present application discloses a processor and a method for executing an instruction on a processor. The method includes: fetching a to-be-executed instruction, the instruction comprising a source address field, a destination address field, an operation type field, and an operation parameter field; determining, in at least one execution unit, an execution unit controlled by a to-be-generated control signal according to the operation type field, determining a source address and a destination address of data operated by the execution unit controlled by the to-be-generated control signal according to the source address field and the destination address field, and determining a data amount of the data operated by the execution unit controlled by the to-be-generated control signal according to the operation parameter field; generating the control signal; and controlling, by using the control signal, the execution unit in the at least one execution unit to execute an operation.
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