-
公开(公告)号：US11537441B2
公开(公告)日：2022-12-27
申请号：US16929970
申请日：2020-07-15
Inventor： Canghai Gu , Peng Wu
Abstract: Embodiments of the present disclosure relate to a method and apparatus for balancing loads, and a computer-readable storage medium. The method includes: for each data processing unit in a set of data processing units in a data processing system, acquiring current input data of the data processing unit for a current clock cycle and next input data of the data processing unit for a next clock cycle; and determining a first metric value indicating changes in input data of said data processing unit in the next clock cycle based on a comparison between the current input data and the next input data. The method further includes controlling an operating state of the set of data processing units in the next clock cycle based on the first metric value determined for the set of data processing units.
-
2.发明申请公开(公告)号：US20200050476A1
公开(公告)日：2020-02-13
申请号：US16505127
申请日：2019-07-08
Inventor： Ningyi Xu , Yan Huang , Jinchen Han , Peng Wu , Jiaxin Shi
Abstract: Embodiments of the present disclosure disclose an artificial intelligence chip and an instruction execution method for an artificial intelligence chip. A specific embodiment of the artificial intelligence chip includes: an instruction memory, a data memory, at least one general execution unit, and at least one dedicated execution unit. The instruction memory is configured to: receive a kernel code including at least one code block. The general execution unit is configured to: receive the code block, lock the dedicated execution unit associated with the received code block, and send an instruction in the received code block to the locked dedicated execution unit. The dedicated execution unit is configured to: execute the received instruction, and store an execution result in the data memory. The data memory is configured to: store the execution result sent by the dedicated execution unit.
-
Patent Agency Ranking
公开(公告)号：US10189426B2
公开(公告)日：2019-01-29
申请号：US15411061
申请日：2017-01-20
Inventor： Zhao Zhang , Jian Ouyang , Jing Wang , Peng Wu , Liang Gao , Yupeng Li
IPC: G06F1/08 , G05D1/00 , G06F1/32 , B60L11/18 , B60R16/023
Abstract: The present application discloses a method and apparatus for operating a field-programmable gate array (FPGA) board in a driverless vehicle. The method according to a specific embodiment includes: collecting driving scenario information on a driving scenario of the driverless vehicle; determining, based on the driving scenario information, a speed at which the driverless vehicle executes a computing operation in the driving scenario; comparing the speed with a speed threshold; switching a working mode of the FPGA board in the driverless vehicle executing the computing operation to reduce power consumption of the FPGA board, in response to the speed being lower than the speed threshold. This embodiment implements the adaptive adjustment of the working mode of the FPGA board, thereby reducing the overall power consumption.
-
4.发明授权公开(公告)号：US11221851B2
公开(公告)日：2022-01-11
申请号：US16936676
申请日：2020-07-23
Inventor： Huimin Li , Peng Wu , Jian Ouyang
Abstract: Embodiments of the present disclosure provide a method, executed by a computing device, for configuring a vector operation, an apparatus, a device, and a storage medium. The method includes obtaining information indicating at least one configurable vector operation parameter. The information indicating the at least one configurable vector operation parameter indicates a type and a value of the configurable vector operation parameter. The method further includes: based on the type and the value of the configurable vector operation parameter, configuring multiple vector operation circuits to enable each of the vector operation circuits to execute a target vector operation including two or more basic vector operations and defined based on the type and value of the configurable vector operation parameter.
-
5.发明授权公开(公告)号：US11372673B2
公开(公告)日：2022-06-28
申请号：US16505127
申请日：2019-07-08
Inventor： Ningyi Xu , Yan Huang , Jinchen Han , Peng Wu , Jiaxin Shi
Abstract: Embodiments of the present disclosure disclose an artificial intelligence chip and an instruction execution method for an artificial intelligence chip. A specific embodiment of the artificial intelligence chip includes: an instruction memory, a data memory, at least one general execution unit, and at least one dedicated execution unit. The instruction memory is configured to: receive a kernel code including at least one code block. The general execution unit is configured to: receive the code block, lock the dedicated execution unit associated with the received code block, and send an instruction in the received code block to the locked dedicated execution unit. The dedicated execution unit is configured to: execute the received instruction, and store an execution result in the data memory. The data memory is configured to: store the execution result sent by the dedicated execution unit.
-
公开(公告)号：US11023391B2
公开(公告)日：2021-06-01
申请号：US16506151
申请日：2019-07-09
Inventor： Peng Wu , Jian Ouyang , Canghai Gu , Wei Qi , Ningyi Xu
Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
-
公开(公告)号：US20200050557A1
公开(公告)日：2020-02-13
申请号：US16506151
申请日：2019-07-09
Inventor： Peng Wu , Jian Ouyang , Canghai Gu , Wei Qi , Ningyi Xu
Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.
-
-
-
-
-
-
Search Results
7
records
(took 0.026 seconds)
