Method and apparatus for generating chip-based computing function, device, and storage medium

    公开(公告)号:US11507348B2

    公开(公告)日:2022-11-22

    申请号:US16711217

    申请日:2019-12-11

    Abstract: Embodiments of the present disclosure provide a method and apparatus for generating a chip-based computing function, a device, and a storage medium. The method includes: acquiring an input parameter value associated with a computing function supported by a chip; determining, based on the input parameter value, at least one candidate computing function template corresponding to the computing function, the candidate computing function template having a configurable parameter associated with performance of the candidate computing function template, and the configurable parameter having at least one candidate value; and determining, according to the input parameter value and candidate values of the configurable parameter of the candidate computing function template, a target computing function template and a target value of a configurable parameter of the target computing function template.

    Processor and method for scaling image

    公开(公告)号:US10922785B2

    公开(公告)日:2021-02-16

    申请号:US16265566

    申请日:2019-02-01

    Abstract: A processor and method for scaling an image are disclosed. A specific embodiment of the processor includes: an off-chip memory, a communication circuit, a control circuit, and an array processor, wherein: the off-chip memory is configured for storing a to-be-scaled original image; the communication circuit is configured for receiving an image scaling instruction; the control circuit is configured for executing the image scaling instruction, and sending a calculation control signal to the array processor; and the array processor is configured for calculating in parallel channel values of N channels in a target pixel using N processing elements in the array processor under the control of the calculation control signal based on a width scaling factor, a height scaling factor, and channel values of N channels in extracted pixel data. The embodiment has improved the processing speed of an image scaling operation.

    Processor and method for executing in-memory copy instructions indicating on-chip or off-chip memory

    公开(公告)号:US10261796B2

    公开(公告)日:2019-04-16

    申请号:US15360245

    申请日:2016-11-23

    Abstract: A processor and a method for executing an instruction on a processor are provided. In the method, a to-be-executed instruction is fetched, the instruction including a source address field, a destination address field, an operation type field, and an operation parameter field; in at least one execution unit, an execution unit controlled by a to-be-generated control signal according to the operation type field is determined, a source address and a destination address of data operated by the execution unit are determined according to the source address field and the destination address field, and a data amount of the data operated by the execution unit controlled by the to-be-generated control signal is determined according to the operation parameter field; the control signal is generated; and the execution unit in the at least one execution unit is controlled by using the control signal.

    Method, apparatus, device and computer-readable storage medium for storage management

    公开(公告)号:US11275683B2

    公开(公告)日:2022-03-15

    申请号:US16942434

    申请日:2020-07-29

    Abstract: Example embodiments of the present disclosure provide a method, an apparatus, a device and a computer-readable storage medium for storage management. The method for storage management includes: obtaining an available channel mode of a plurality of channels in a memory of a data processing system, the available channel mode indicating availabilities of the plurality of channels, and each of the plurality of channels being associated with a set of addresses in the memory; obtaining a channel data-granularity of the plurality of channels, the channel data-granularity indicating a size of a data block that can be carried on each channel; obtaining a target address of data to be transmitted in the memory; and determining a translated address corresponding to the target address based on the available channel mode and the channel data-granularity.

    Method, system and apparatus for storing website private key plaintext

    公开(公告)号:US10951595B2

    公开(公告)日:2021-03-16

    申请号:US15618655

    申请日:2017-06-09

    Abstract: The present application discloses a method, system and apparatus for storing a website private key plaintext. A specific implementation of the method includes: receiving a public key sent from a terminal configured to perform encryption and decryption, wherein the public key is generated at random by the terminal; encrypting a website private key plaintext by using the public key to generate a website private key ciphertext, wherein the website private key plaintext is pre-acquired; and sending the website private key ciphertext to the terminal, so that the terminal decrypts the website private key ciphertext by using the private key to generate the website private key plaintext and store the website private key plaintext in the terminal. This implementation improves the security of storage of the website private key plaintext.

    Method and apparatus for executing instruction for artificial intelligence chip

    公开(公告)号:US10891134B2

    公开(公告)日:2021-01-12

    申请号:US16505913

    申请日:2019-07-09

    Abstract: Embodiments of the present disclosure disclose a method and apparatus for executing an instruction for an artificial intelligence chip. A specific embodiment of the method comprises: receiving descriptive information for describing a neural network model sent by a central processing unit, the descriptive information including at least one operation instruction; analyzing the descriptive information to acquire the at least one operation instruction; determining, for an operation instruction of the at least one operation instruction, a special-purpose execution component executing the operation instruction, and locking the determined special-purpose execution component; sending the operation instruction to the determined special-purpose execution component; and unlocking the determined special-purpose execution component in response to receiving a notification for instructing the operation instruction being completely executed.

    PROCESSOR AND METHOD FOR SCALING IMAGE
    7.
    发明申请

    公开(公告)号:US20190164254A1

    公开(公告)日:2019-05-30

    申请号:US16265566

    申请日:2019-02-01

    Abstract: A processor and method for scaling an image are disclosed. A specific embodiment of the processor includes: an off-chip memory, a communication circuit, a control circuit, and an array processor, wherein: the off-chip memory is configured for storing a to-be-scaled original image; the communication circuit is configured for receiving an image scaling instruction; the control circuit is configured for executing the image scaling instruction, and sending a calculation control signal to the array processor; and the array processor is configured for calculating in parallel channel values of N channels in a target pixel using N processing elements in the array processor under the control of the calculation control signal based on a width scaling factor, a height scaling factor, and channel values of N channels in extracted pixel data. The embodiment has improved the processing speed of an image scaling operation.

    Method and apparatus for processing data sequence

    公开(公告)号:US11087203B2

    公开(公告)日:2021-08-10

    申请号:US15618415

    申请日:2017-06-09

    Abstract: The present application discloses a method and apparatus for processing a data sequence. A specific implementation of the method includes: receiving an inputted to-be-processed data sequence; copying a weight matrix in a recurrent neural network model to an embedded block random access memory (RAM) of a field-programmable gate array (FPGA); processing sequentially each piece of to-be-processed data in the to-be-processed data sequence by using an activation function in the recurrent neural network model and the weight matrix stored in the embedded block RAM; and outputting a processed data sequence corresponding to the to-be-processed data sequence. This implementation improves the data sequence processing efficiency of the recurrent neural network model.

    Data processing method and apparatus

    公开(公告)号:US11023801B2

    公开(公告)日:2021-06-01

    申请号:US15618817

    申请日:2017-06-09

    Abstract: The present application discloses a data processing method and apparatus. A specific implementation of the method includes: receiving floating point data sent from an electronic device; converting the received floating point data into fixed point data according to a data length and a value range of the received floating point data; performing calculation on the obtained fixed point data according to a preset algorithm to obtain result data in a fixed point form; and converting the obtained result data in the fixed point form into result data in a floating point form and sending the result data in the floating point form to the electronic device. This implementation improves the data processing efficiency.

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