公开(公告)号：US12165956B2

公开(公告)日：2024-12-10

申请号：US17643247

申请日：2021-12-08

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Menglu Li ,  Raymundo M. Camenforte ,  Scott D. Morrison

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L25/16 ,  H01L49/02

Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.

公开(公告)号：US12107283B2

公开(公告)日：2024-10-01

申请号：US17484471

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Angelo V. Marasco ,  Nathan J. Bohney ,  John M. McCambridge ,  Antonio Manenti ,  Laura E. Mayer ,  Scott L. Gooch ,  Jonathan C. Wilson ,  Flynn P. Carson

IPC: H01M50/183 ,  H01M10/42 ,  H01M50/40 ,  H01M50/531 ,  H01M50/543

CPC classification number: H01M50/183 ,  H01M10/425 ,  H01M50/40 ,  H01M50/531 ,  H01M50/543 ,  H01M2010/4271 ,  H01M2220/30

Abstract: Battery systems according to embodiments of the present technology may include a battery cell having an electrode tab extending from an edge of the battery cell. The systems may also include a module electrically coupled with the battery cell. The module may be characterized by a first surface, a height, and a second surface opposite the first surface. A conductive tab coupled along the first surface of the module may extend from a first end parallel to a plane of the first surface. The conductive tab may be characterized by a curvature proximate a midpoint of the conductive tab. A distal region of the conductive tab may return back across the first surface of the module substantially parallel to the first surface. A distal portion of the electrode tab may be fixedly coupled with the distal region of the conductive tab.

公开(公告)号：US20230178458A1

公开(公告)日：2023-06-08

申请号：US17643247

申请日：2021-12-08

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Menglu Li ,  Raymundo M. Camenforte ,  Scott D. Morrison

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/538 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/4952 ,  H01L23/31 ,  H01L23/5381 ,  H01L23/53228 ,  H01L28/00

Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.

公开(公告)号：US20220157680A1

公开(公告)日：2022-05-19

申请号：US16952567

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Flynn P. Carson ,  Jun Zhai ,  Raymundo M. Camenforte ,  Menglu Li

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：US20220071013A1

公开(公告)日：2022-03-03

申请号：US17005607

申请日：2020-08-28

Applicant: Apple Inc.

Inventor： Scott D. Morrison ,  Karthik Shanmugam ,  Raymundo M. Camenforte ,  Rakshit Agrawal ,  Flynn P. Carson ,  Kiranjit Dhaliwal

IPC: H05K1/18 ,  H01L23/00

Abstract: Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.

公开(公告)号：US10115677B2

公开(公告)日：2018-10-30

申请号：US15630346

申请日：2017-06-22

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L29/00 ,  H01L23/552 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

公开(公告)号：US20170301631A1

公开(公告)日：2017-10-19

申请号：US15630346

申请日：2017-06-22

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/528

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

公开(公告)号：US09589936B2

公开(公告)日：2017-03-07

申请号：US14619002

申请日：2015-02-10

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Flynn P. Carson

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/552 ,  H01L25/03 ,  H01L23/525

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/552 ,  H01L24/19 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2224/81

Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.

Abstract translation: 描述了扇出晶片级封装（FOWLP）和形成方法。 在一个实施例中，包装包括第一布线层，第一布线层的顶侧上的第一管芯，以及将第一管芯封装在第一布线层上的第一模制化合物。 第一多个导电柱从第一路由层的底侧延伸。 第二管芯位于第二布线层的顶侧，并且第一多个导电柱位于布线层的顶侧。 第二模塑料在第二路由层上封装第一模塑料，第一路由层，第一多个导电柱和第二模。 在一个实施例中，多个导电凸块（例如焊球）从第二布线层的底侧延伸。