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公开(公告)号：US20180364782A1
公开(公告)日：2018-12-20
申请号：US16011476
申请日：2018-06-18
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Leonardo De Paula Rosa Piga , Samuel Naffziger , Ivan Matosevic , Indrani Paul
IPC: G06F1/32
Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
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公开(公告)号：US20170293564A1
公开(公告)日：2017-10-12
申请号：US15094391
申请日：2016-04-08
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Ihab Amer , Khaled Mammou , Haibo Liu , Edward Harold , Fabio Gulino , Samuel Naffziger , Gabor Sines , Lawrence A. Bair , Andy Sung , Lei Zhang
IPC: G06F12/08 , G11C11/417
CPC classification number: G06F12/0877 , G06F12/0893 , G06F2212/1028 , G06F2212/221 , G06F2212/60 , G11C5/148 , G11C11/417
Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.
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公开(公告)号：US09772676B2
公开(公告)日：2017-09-26
申请号：US14190803
申请日：2014-02-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen Kosonocky , Samuel Naffziger
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/3206 , Y02D10/16 , Y02D10/172
Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.
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公开(公告)号：US09483092B2
公开(公告)日：2016-11-01
申请号：US14053315
申请日：2013-10-14
Applicant: Advanced Micro Devices, Inc.
Inventor： Samuel Naffziger , Baomin Liu , Maxat Touzelbaev
CPC classification number: G06F1/26 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126 , Y02D10/16
Abstract: An integrated circuit includes a multiple number of processor cores and a system management unit. The multiple number of processor cores each operate at one of a multiple number of performance states. The system management unit is coupled to the multiple number of processor cores, for setting performance states of the multiple number of processor cores. The system management unit boosts a first performance state of a first processor core of the multiple number of processor cores based on both a first temperature calculated from an estimated power consumption, and a second temperature based on a temperature measurement.
Abstract translation: 集成电路包括多个处理器核和系统管理单元。 多个处理器核心各自以多个性能状态中的一个操作。 系统管理单元耦合到多个处理器核心，用于设置多个处理器核心的性能状态。 系统管理单元基于从估计的功耗计算出的第一温度和基于温度测量的第二温度来提高多个处理器核心的第一处理器核心的第一性能状态。
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公开(公告)号：US09170631B2
公开(公告)日：2015-10-27
申请号：US13759611
申请日：2013-02-05
Applicant: Advanced Micro Devices, Inc.
Inventor： Samuel Naffziger , Bao-min Liu
CPC classification number: G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: Methods, apparatus, and fabrication processes relating to thermal calculations of an integrated circuit device are reported. The methods may comprise determining a power consumption by a power entity of an integrated circuit, the power entity comprising at least one functional element of the integrated circuit; determining a temperature of a thermal entity, the thermal entity comprising a subset of the power entity; and adjusting at least one of a voltage or an operating frequency of at least one functional element of the power entity, based upon the temperature of the thermal entity being greater than or equal to a predetermined threshold temperature for the thermal entity.
Abstract translation: 报告了与集成电路装置的热计算相关的方法，装置和制造过程。 所述方法可以包括确定集成电路的功率实体的功率消耗，所述功率实体包括所述集成电路的至少一个功能元件; 确定热实体的温度，所述热实体包括所述功率实体的子集; 以及基于所述热实体的温度大于或等于所述热实体的预定阈值温度来调节所述功率实体的至少一个功能元件的电压或工作频率中的至少一个。
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Patent Agency Ranking
公开(公告)号：US20140223199A1
公开(公告)日：2014-08-07
申请号：US13759611
申请日：2013-02-05
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Samuel Naffziger
IPC: G06F1/26
CPC classification number: G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: Methods, apparatus, and fabrication processes relating to thermal calculations of an integrated circuit device are reported. The methods may comprise determining a power consumption by a power entity of an integrated circuit, the power entity comprising at least one functional element of the integrated circuit; determining a temperature of a thermal entity, the thermal entity comprising a subset of the power entity; and adjusting at least one of a voltage or an operating frequency of at least one functional element of the power entity, based upon the temperature of the thermal entity being greater than or equal to a predetermined threshold temperature for the thermal entity.
Abstract translation: 报告了与集成电路装置的热计算相关的方法，装置和制造过程。 所述方法可以包括确定集成电路的功率实体的功率消耗，所述功率实体包括所述集成电路的至少一个功能元件; 确定热实体的温度，所述热实体包括所述功率实体的子集; 以及基于所述热实体的温度大于或等于所述热实体的预定阈值温度来调节所述功率实体的至少一个功能元件的电压或工作频率中的至少一个。
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公开(公告)号：US20250117352A1
公开(公告)日：2025-04-10
申请号：US18910202
申请日：2024-10-09
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Alan D. Smith , Michael Mantor , Mark Fowler , Vydhyanathan Kalyanasundharam , Samuel Naffziger
IPC: G06F13/40 , G06F9/50 , G06F12/0893
Abstract: A processing system includes one or more accelerator units (AUs) each having a modular architecture. To this end, each AU includes a connection circuitry and one or more memory stacks disposed on the connection circuitry. Further, each AU includes one or more interposer dies each disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to a corresponding memory stack of the memory stacks via the connection circuitry. Further, each interposer die of each AU includes circuitry configured to concurrently support two or more types of compute dies.
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公开(公告)号：US12266585B2
公开(公告)日：2025-04-01
申请号：US17516988
申请日：2021-11-02
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： John Wuu , Samuel Naffziger , Patrick J. Shyvers , Milind S. Bhagavat , Kaushik Mysore , Brett P. Wilkerson
IPC: H01L23/367 , H01L23/36 , H01L25/00 , H01L25/065 , H01L23/373
Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
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公开(公告)号：US20240324248A1
公开(公告)日：2024-09-26
申请号：US18474179
申请日：2023-09-25
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： John Wuu , Kevin Gillespie , Samuel Naffziger , Spence Oliver , Rajit Seahra , Regina T. Schmidt , Raja Swaminathan , Omar Zia
IPC: H10B80/00 , H01L23/544 , H01L25/00 , H01L25/18
CPC classification number: H10B80/00 , H01L23/544 , H01L25/18 , H01L25/50 , H01L23/481 , H01L23/5286 , H01L24/06 , H01L24/08 , H01L2223/54433 , H01L2224/06181 , H01L2224/08145
Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11841803B2
公开(公告)日：2023-12-12
申请号：US16456287
申请日：2019-06-28
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Skyler J. Saleh , Samuel Naffziger , Milind S. Bhagavat , Rahul Agarwal
IPC: G06F12/08 , G06F12/0897 , G06F13/40 , G06F13/16
CPC classification number: G06F12/0897 , G06F13/1668 , G06F13/4027 , G06F2212/1024
Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.
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