公开(公告)号：US20200286778A1

公开(公告)日：2020-09-10

申请号：US16882177

申请日：2020-05-22

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Wayne MCMILLAN ,  Rutger MEYER TIMMERMAN THIJSSEN ,  Naamah ARGAMAN ,  Tapashree ROY ,  Sage Toko Garrett DOSHAY

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L25/04 ,  H01L25/16

Abstract: Systems and methods herein are related to the formation of optical devices including stacked optical element layers using silicon wafers, glass, or devices as substrates. The optical elements discussed herein can be fabricated on temporary or permanent substrates. In some examples, the optical devices are fabricated to include transparent substrates or devices including charge-coupled devices (CCD), or complementary metal-oxide semiconductor (CMOS) image sensors, light-emitting diodes (LED), a micro-LED (uLED) display, organic light-emitting diode (OLED) or vertical-cavity surface-emitting laser (VCSELs). The optical elements can have interlayers formed in between optical element layers, where the interlayers can range in thickness from 1 nm to 3 mm.

公开(公告)号：US20200003937A1

公开(公告)日：2020-01-02

申请号：US16120707

申请日：2018-09-04

Applicant: Applied Materials, Inc.

Inventor： Jinxin FU ,  Ludovic GODET ,  Wayne MCMILLAN

IPC: G02B5/18 ,  G03F7/00 ,  C23C16/40 ,  C23C16/56

Abstract: Embodiments of the present disclosure generally relate to a method for forming an optical component, for example, for a virtual reality or augmented reality display device. In one embodiment, the method includes forming a first layer having a pattern on a substrate, and the first layer has a first refractive index. The method further includes forming a second layer on the first layer by a flowable chemical vapor deposition (FCVD) process, and the second layer has a second refractive index less than the first refractive index.

公开(公告)号：US20200003936A1

公开(公告)日：2020-01-02

申请号：US16120733

申请日：2018-09-04

Applicant: Applied Materials, Inc.

Inventor： Jinxin FU ,  Ludovic GODET ,  Wayne MCMILLAN

IPC: G02B5/18 ,  G03F7/00

Abstract: Embodiments of the present disclosure generally relate to a method for forming an optical component, for example, for a virtual reality or augmented reality display device. In one embodiment, the method includes forming a first layer on a substrate, and the first layer has a first refractive index. The method further includes pressing a stamp having a pattern onto the first layer, and the pattern of the stamp is transferred to the first layer to form a patterned first layer. The method further includes forming a second layer on the patterned first layer by spin coating, and the second layer has a second refractive index greater than the first refractive index. The second layer having the high refractive index is formed by spin coating, leading to improved nanoparticle uniformity in the second layer.

公开(公告)号：US20170088949A1

公开(公告)日：2017-03-30

申请号：US14957440

申请日：2015-12-02

Applicant: Applied Materials, Inc.

Inventor： Viachslav BABAYAN ,  Qiwei LIANG ,  Tobin KAUFMAN-OSBORN ,  Ludovic GODET ,  Srinivas D. NEMANI

IPC: C23C16/448 ,  C23C16/44 ,  C23C16/458 ,  H01L21/687 ,  C23C16/46

CPC classification number: C23C16/4485 ,  C23C16/4401 ,  C23C16/4411 ,  C23C16/45517 ,  C23C16/4586 ,  C23C16/46 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67742 ,  H01L21/67754 ,  H01L21/68707 ,  H01L21/68764 ,  H01L21/68771

Abstract: The present disclosure generally relate to a semiconductor processing apparatus. In one embodiment, a processing chamber is disclosed herein. The processing chamber includes a chamber body and lid defining an interior volume, the lid configured to support a housing having a cap, a substrate support disposed in the interior volume, a vaporizer coupled to the cap and having an outlet open to the interior volume of the processing chamber, wherein the vaporizer is configured to deliver a precursor gas to a processing region defined between the vaporizer and the substrate support, and a heater disposed adjacent to the vaporizer, wherein the heater is configured to heat the vaporizer.

公开(公告)号：US20160291476A1

公开(公告)日：2016-10-06

申请号：US14677552

申请日：2015-04-02

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Sang Ki NAM ,  Christine Y. OUYANG

IPC: G03F7/40

CPC classification number: G03F7/38

Abstract: Embodiments described herein generally relate to methods for mitigating patterning defects. More specifically, embodiments described herein relate to utilizing field guided post exposure bake processes to mitigate microbridge photoresist defects. An electric field may be applied to a substrate being processed during a post exposure bake process. Photoacid generated as a result of the exposure may be moved along a direction defined by the electric field. The movement of the photoacid may contact microbridge defects and facilitate the removal of the microbridge defects from the surface of a substrate.

Abstract translation: 本文描述的实施方案一般涉及减轻图案化缺陷的方法。 更具体地，本文所述的实施例涉及利用场引导后曝光烘烤工艺来减轻微桥光刻胶缺陷。 可以在后曝光烘烤处理中将电场施加到正在处理的基板。 作为曝光结果产生的光酸可以沿着由电场限定的方向移动。 光致酸的运动可能会接触微桥缺陷，并有助于从基片的表面去除微桥缺陷。

公开(公告)号：US20160204029A1

公开(公告)日：2016-07-14

申请号：US14975028

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki MEBARKI ,  Annamalai LAKSHMANAN ,  Kaushal K. SINGH ,  Paul F. MA ,  Mehul B. NAIK ,  Andrew COCKBURN ,  Ludovic GODET

IPC: H01L21/768 ,  H01L21/285

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide stack comprising as plurality of metal silicide layers on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide stack in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer.

Abstract translation: 提供了用于形成用于半导体应用的后端互连结构的纳米线的金属硅化物的方法和装置。 在一个实施例中，该方法包括通过化学气相沉积工艺或物理气相沉积工艺在衬底上形成包含多个金属硅化物层的金属硅化物堆叠，对处理室中的金属硅化物堆进行热处理，施加微波功率 在处理室中，同时热处理金属硅化物层; 并且在热处理金属硅化物层的同时保持低于400摄氏度的衬底温度。

公开(公告)号：US20160141202A1

公开(公告)日：2016-05-19

申请号：US14597149

申请日：2015-01-14

Applicant: Applied Materials, Inc.

Inventor： Jun XUE ,  Ludovic GODET ,  Erica CHEN ,  Srinivas D. NEMANI ,  Ellie Y. YIEH

IPC: H01L21/768 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/223

CPC classification number: H01L21/7682 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32412 ,  H01J37/32422 ,  H01L21/2236 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/768 ,  H01L21/76825 ,  H01L23/5222

Abstract: Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.

Abstract translation: 提供了使用离子注入工艺形成在互连结构的不同位置上形成的所需材料的互连结构中的空气间隙以限定蚀刻边界，然后进行半导体器件的蚀刻工艺的方法。 在一个实施例中，一种用于在衬底上形成互连结构中的气隙的方法，所述方法包括将离子注入设置在衬底上的绝缘材料的第一区域中，留下没有注入离子的第二区域，第二区域具有第一 与第一区域接合的表面和与衬底接合的第二表面，以及执行蚀刻工艺以选择性地蚀刻第二区域远离衬底，在第一区域和衬底之间形成气隙。

公开(公告)号：US20160011526A1

公开(公告)日：2016-01-14

申请号：US14476944

申请日：2014-09-04

Applicant: Applied Materials, Inc.

Inventor： Peng XIE ,  Ludovic GODET

IPC: G03F7/20

CPC classification number: G03F7/38 ,  G03F7/2022 ,  G03F7/70325

Abstract: Methods disclosed herein apply an electric field and/or a magnetic field during photolithography processes. The field application may control the diffusion of the charged species generated by the photoacid generator along the line and spacing direction, preventing the line edge/width roughness that results from random diffusion. The field application may additionally or alternatively control the diffusion of the charged species in a direction perpendicular to a plane formed by the photoresist layer. Such controlled perpendicular diffusion may increase the photoresist sensitivity. In other embodiments, the field may control the diffusion of the charged species within the plane of the photoresist layer but in a direction perpendicular or non-parallel to the line and spacing direction. Apparatuses for carrying out the aforementioned methods are also disclosed herein.

Abstract translation: 本文公开的方法在光刻工艺期间施加电场和/或磁场。 场应用可以控制由光致酸发生器沿着线和间隔方向产生的带电物质的扩散，从而防止由随机扩散引起的线边缘/宽度粗糙度。 场应用可以附加地或替代地控制带电物质在垂直于由光致抗蚀剂层形成的平面的方向上的扩散。 这种受控的垂直扩散可以增加光致抗蚀剂的灵敏度。 在其他实施例中，场可以控制带电物质在光致抗蚀剂层的平面内但在垂直于或不平行于线和间隔方向的方向上的扩散。 用于实施上述方法的装置也在此公开。

公开(公告)号：US20160005662A1

公开(公告)日：2016-01-07

申请号：US14736020

申请日：2015-06-10

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. YIEH ,  Huixiong DAI ,  Srinivas D. NEMANI ,  Ludovic GODET ,  Christopher Dennis BENCHER

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/20

Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.

Abstract translation: 本公开的实施例提供了使用电子或离子注入的用于覆盖和边缘放置误差（EPE）的局部应力调制的装置和方法。 在一个实施例中，用于校正衬底上的覆盖误差的处理通常包括在衬底上的度量工具中执行测量过程以获得衬底失真或覆盖误差图，基于所述衬底失真或覆盖误差图确定掺杂参数以校正重叠误差或衬底失真 覆盖误差图，并且基于确定用于校正衬底失真或重叠误差的掺杂参数向掺杂装置提供掺杂配方。 实施例还可以使用确定的掺杂修复配方在衬底上执行掺杂处理过程，例如通过将覆盖误差图或衬底失真与存储在计算系统中的数据库进行比较。

公开(公告)号：US20150136732A1

公开(公告)日：2015-05-21

申请号：US14547702

申请日：2014-11-19

Applicant: Applied Materials, Inc.

Inventor： Xianmin TANG ,  Ludovic GODET ,  Guojun LIU ,  Jing TANG ,  Phillip STOUT ,  Rong TAO

IPC: C23C16/56 ,  C23C14/50 ,  C23C16/458 ,  C23C14/00

CPC classification number: C23C14/046

Abstract: A method and apparatus for depositing films on a substrate is described. The method includes depositing a film on a substrate with feature formed therein or thereon. The feature includes a first surface and a second surface that are at different levels. A least a portion of the deposited film is removed by exposing the substrate to an ion flux from a linear ion source. The ion flux has an ion angular spread of less than or equal to 90 degrees and greater than or equal to 15 degrees. In certain embodiments, the feature can be a nanoscale, high aspect ratio feature such as narrow, deep trench, a small diameter, deep hole, or a dual damascene structure. Such features are often found in integrated circuit devices.

Abstract translation: 描述了一种在衬底上沉积膜的方法和装置。 该方法包括在其上或其上形成特征的基底上沉积膜。 该特征包括处于不同水平的第一表面和第二表面。 通过将衬底暴露于来自线性离子源的离子通量来去除沉积膜的至少一部分。 离子通量具有小于或等于90度且大于或等于15度的离子角度扩展。 在某些实施例中，特征可以是纳米尺度的高纵横比特征，例如窄的，深的沟槽，小直径，深孔或双镶嵌结构。 这些特征通常在集成电路器件中找到。