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    Memory device bandwidth optimization
    21.
    发明授权
    Memory device bandwidth optimization 有权

    公开(公告)号：US11914532B2

    公开(公告)日：2024-02-27

    申请号：US17655324

    申请日：2022-03-17

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil

    IPC: G06F13/16 ,  G06F1/06

    CPC classification number: G06F13/1684 ,  G06F1/06 ,  G06F13/1647

    Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

    Multi-activation techniques for partial write operations
    22.
    发明授权
    Multi-activation techniques for partial write operations 有权

    公开(公告)号：US11847348B2

    公开(公告)日：2023-12-19

    申请号：US17410657

    申请日：2021-08-24

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0676 ,  G06F3/0677 ,  G06F3/0679

    Abstract: Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

    Reset extender for divided clock domains
    28.
    发明授权
    Reset extender for divided clock domains 有权
    为分时钟域复位扩展器

    公开(公告)号：US08786332B1

    公开(公告)日：2014-07-22

    申请号：US13744004

    申请日：2013-01-17

    Applicant: Apple Inc.

    Inventor： Erik P. Machnicki ,  David S. Warren ,  Shane J. Keil ,  Sukalpa Biswas

    IPC: H03L7/00 ,  G06F1/24

    CPC classification number: G06F1/24 ,  G06F1/10 ,  H03L5/00

    Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

    Abstract translation: 时钟分频器可以向逻辑块部分提供较低速度的时钟，但是在复位期间，时钟分频器可能无法正常工作，导致逻辑块部分在大于设计该逻辑的频率的时钟频率下复位。 然而，可以采用扩展复位，其中时钟分频器首先在逻辑块部分之前正常复位，从而允许根据分频时钟（例如，而不是更高速度的时钟）来复位该逻辑。 还可以采用异步复位，其中一个或多个时钟分频器首先在被提供有（同步的）高速时钟信号之前从复位中出现，使得时钟分频器彼此同相。 这可以使IC之间的不同区域之间的通信可能不会彼此正确相位。

    RESET EXTENDER FOR DIVIDED CLOCK DOMAINS
    29.
    发明申请
    RESET EXTENDER FOR DIVIDED CLOCK DOMAINS 有权
    复位扩展器用于分开的时钟域

    公开(公告)号：US20140197870A1

    公开(公告)日：2014-07-17

    申请号：US13744004

    申请日：2013-01-17

    Applicant: APPLE INC.

    Inventor： Erik P. Machnicki ,  David S. Warren ,  Shane J. Keil ,  Sukalpa Biswas

    IPC: H03L5/00

    CPC classification number: G06F1/24 ,  G06F1/10 ,  H03L5/00

    Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

    Abstract translation: 时钟分频器可以向逻辑块部分提供较低速度的时钟，但是在复位期间，时钟分频器可能无法正常工作，导致逻辑块部分在大于设计该逻辑的频率的时钟频率下复位。 然而，可以采用扩展复位，其中时钟分频器首先在逻辑块部分之前正常复位，从而允许根据分频时钟（例如，而不是更高速度的时钟）来复位该逻辑。 还可以采用异步复位，其中一个或多个时钟分频器首先在被提供有（同步的）高速时钟信号之前从复位中出现，使得时钟分频器彼此同相。 这可以使IC之间的不同区域之间的通信可能不会彼此正确相位。

    Interfacing Dynamic Hardware Power Managed Blocks and Software Power Managed Blocks
    30.
    发明申请
    Interfacing Dynamic Hardware Power Managed Blocks and Software Power Managed Blocks 有权
    动态硬件电源管理块和软件电源管理块的接口

    公开(公告)号：US20140173307A1

    公开(公告)日：2014-06-19

    申请号：US13719535

    申请日：2012-12-19

    Applicant: APPLE INC.

    Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

    IPC: G06F1/32

    CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

    Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

    Abstract translation: 公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。 在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。 功能单元可以通过硬件，软件或两者进行功率管理。 每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。 链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。 响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

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