公开(公告)号：US10318377B2

公开(公告)日：2019-06-11

申请号：US16029829

申请日：2018-07-09

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Sukalpa Biswas ,  Jeffrey R. Wilcox ,  Farid Nemati

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/1072 ,  G06F12/121 ,  G06F12/06 ,  G06F12/126 ,  G11C29/04 ,  G11C29/44 ,  G11C29/00 ,  G06F12/12

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

公开(公告)号：US20180107240A1

公开(公告)日：2018-04-19

申请号：US15831732

申请日：2017-12-05

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09747239B2

公开(公告)日：2017-08-29

申请号：US14467164

申请日：2014-08-25

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Munetoshi Fukami ,  Manu Gulati

IPC: G06F1/00 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4022 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.

公开(公告)号：US09529403B2

公开(公告)日：2016-12-27

申请号：US14466205

申请日：2014-08-22

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Parin Patel ,  Keith Cox ,  Derek Iwamoto ,  Cyril de la Cropte de Chanterac ,  Christopher J. Young

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3296 ,  Y02D10/172

Abstract: A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Abstract translation: 公开了一种用于提供用于功率控制功能的遥测的方法和装置。 一种系统包括具有第一电源管理电路的集成电路（IC）。 IC还包括多个不同功率域内的多个功能电路块。 第二电源管理电路在IC外部实现并且包括多个电压调节器。 每个电源域被耦合以从一个电压调节器接收电力。 在操作期间，第一电源管理电路可以发送请求改变提供给IC的一个或多个电压的命令。 第二电力管理电路可以通过执行所请求的电压变化来响应，并且还可以向第一电力管理电路提供遥测数据。 第二电力管理电路还可以响应于从第一电力管理电路接收无操作命令来提供遥测数据。

公开(公告)号：US09280471B2

公开(公告)日：2016-03-08

申请号：US14081549

申请日：2013-11-15

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US20160054788A1

公开(公告)日：2016-02-25

申请号：US14466315

申请日：2014-08-22

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Parin Patel ,  Derek Iwamoto ,  Carl D. Tappan

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3209 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/172

Abstract: A method and apparatus for parameter-based sensor selection is disclosed. In one embodiment, a system includes an integrated circuit (IC) having a first power management circuit, and a second power management circuit external to the IC. The IC includes various functional units implemented in various power domains, while the second power management circuit (which may be implemented on an IC) includes a number of voltage regulators for providing power to the power domains. The second power management circuit also includes sensors that provide data about a system parameter, with the data being provided at telemetry to the first power management circuit. When the system parameter is less than a first threshold, the telemetry data may be based on a first sensor. When the system parameter is greater than the first threshold, the telemetry data may be based on a second sensor.

Abstract translation: 公开了一种用于基于参数的传感器选择的方法和装置。 在一个实施例中，系统包括具有第一电源管理电路的集成电路（IC）和IC外部的第二电源管理电路。 IC包括实现在各种功率域中的各种功能单元，而第二功率管理电路（其可以在IC上实现）包括用于向电力域提供电力的多个电压调节器。 第二电力管理电路还包括提供关于系统参数的数据的传感器，数据在遥测中提供给第一电力管理电路。 当系统参数小于第一阈值时，遥测数据可以基于第一传感器。 当系统参数大于第一阈值时，遥测数据可以基于第二传感器。

公开(公告)号：US09261939B2

公开(公告)日：2016-02-16

申请号：US13890306

申请日：2013-05-09

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Pulkit Desai ,  Rong Zhang Hu

IPC: G06F1/32 ,  G06F3/14 ,  G09G5/00 ,  G09G5/393 ,  G09G5/395

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

公开(公告)号：US20160029318A1

公开(公告)日：2016-01-28

申请号：US14444198

申请日：2014-07-28

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Gilbert H. Herbeck

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  H04W52/0212 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/26

Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.

Abstract translation: 一种用于管理系统中的电力的方法，其中所述系统可以包括被配置为传送串行数据的第一设备和耦合到所述第一设备的第二设备。 第二设备可以包括收发器和中断逻辑，并且可以被配置为激活中断逻辑并使能收发器的降低的功率模式。 以降低功率模式工作的收发器的功耗可能小于工作模式下收发器的功耗。 第二设备还可以被配置为响应于第二设备的输入的电压电平的变化来断言中断信号，然后响应于断言中断信号的断言而使得收发器的功率降低模式失效。

公开(公告)号：US20150347287A1

公开(公告)日：2015-12-03

申请号：US14458949

申请日：2014-08-13

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. De Cesare ,  Anand Dalal

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0223 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0634 ,  G06F3/0673 ,  G06F9/4406 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/1032 ,  G11C11/40615 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

公开(公告)号：US20140089546A1

公开(公告)日：2014-03-27

申请号：US13629509

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Josh P. de Cesare ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

Abstract translation: 一种用于保持精确中断时间戳的系统和方法。 半导体芯片包括具有多个中断源的接口的中断控制器（IC）。 响应于接收到中断，IC复制并记录存储在用于维持全局经过时间的主时基计数器中的值。 IC向对应的处理器发送中断指示。 中断服务程序（ISR）或设备驱动程序请求与中断相关联的时间戳。 处理器不是向操作系统发送请求以获得存储在主时基计数器中的当前值，而是从IC请求记录的时间戳。 IC识别与中断相关联的存储时间戳，并将其返回给处理器。