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    Reducing latency in a peripheral component interconnect express link
    21.
    发明授权
    Reducing latency in a peripheral component interconnect express link 有权
    减少外设组件互连中的延迟快速链接

    公开(公告)号：US09015396B2

    公开(公告)日：2015-04-21

    申请号：US13622266

    申请日：2012-09-18

    Applicant: Apple Inc.

    Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

    IPC: G06F13/24 ,  G06F1/32 ,  G06F1/00

    CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

    Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。

    Timestamp based display update mechanism
    22.
    发明授权
    Timestamp based display update mechanism 有权

    公开(公告)号：US11211036B2

    公开(公告)日：2021-12-28

    申请号：US16919495

    申请日：2020-07-02

    Applicant: Apple Inc.

    Inventor： Brijesh Tripathi ,  Arthur L. Spence ,  Joshua P. de Cesare ,  Ilie Garbacea ,  Guy Cote ,  Mahesh B. Chappalli ,  Malcolm D. Gray ,  Christopher P. Tann

    IPC: G09G5/39 ,  G09G5/395 ,  G06F3/14 ,  G06F3/147

    Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

    System on a chip with fast wake from sleep
    24.
    发明授权
    System on a chip with fast wake from sleep 有权

    公开(公告)号：US10571996B2

    公开(公告)日：2020-02-25

    申请号：US15691903

    申请日：2017-08-31

    Applicant: Apple Inc.

    Inventor： Anand Dalal ,  Joshua P. de Cesare

    IPC: G06F1/32 ,  G06F9/4401 ,  G06F9/445 ,  G06F1/3287 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3231 ,  G06F1/3293

    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

    Techniques for adjusting computing device sleep states using onboard sensors and learned user behaviors
    25.
    发明授权
    Techniques for adjusting computing device sleep states using onboard sensors and learned user behaviors 有权

    公开(公告)号：US10423212B2

    公开(公告)日：2019-09-24

    申请号：US15817113

    申请日：2017-11-17

    Applicant: Apple Inc.

    Inventor： Joshua P. de Cesare ,  Jonathan J. Andrews ,  Jeffrey R. Wilcox

    IPC: G06F1/32 ,  H04W4/02 ,  G06F1/3231 ,  G06Q10/10 ,  G06F1/3203

    Abstract: This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.

    Methods and Systems for Time Keeping in a Data Processing System
    30.
    发明申请
    Methods and Systems for Time Keeping in a Data Processing System 审中-公开
    时间保持在数据处理系统中的方法和系统

    公开(公告)号：US20140164661A1

    公开(公告)日：2014-06-12

    申请号：US14159705

    申请日：2014-01-21

    Applicant: Apple Inc.

    Inventor： Joshua P. de Cesare ,  Bernard Joseph Semeria ,  Michael John Smith

    IPC: G06F1/32 ,  G06F13/24

    CPC classification number: G06F1/3287 ,  G06F9/4825 ,  G06F13/24 ,  G06F13/36 ,  Y02D10/14 ,  Y02D10/24

    Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

    Abstract translation: 具有中断的数据处理系统和用于操作这种数据处理系统的方法和用于引起这种方法并包含可执行程序指令的机器可读介质。 在一个实施例中，示例性数据处理系统包括处理系统，耦合到处理系统的中断控制器和耦合到中断控制器的定时器电路。 中断控制器被配置为向处理系统提供第一中断信号和第二中断信号。 处理系统被配置为维持多个进程的时间相关事件的数据结构（例如，列表），并且处理系统被配置为对代表一段时间的值的输入进行加密， 进入定时器电路。 定时器电路被配置为响应于该时间段的到期而导致第一中断信号的断言。

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