公开(公告)号：US20080012115A1

公开(公告)日：2008-01-17

申请号：US11891867

申请日：2007-08-13

Applicant: Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

Inventor： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Abstract translation: 一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层， 至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

公开(公告)号：US20070253143A1

公开(公告)日：2007-11-01

申请号：US11415039

申请日：2006-05-01

Applicant: Haim Goldberger ,  Reuven Katraro ,  Doron Gozaly

Inventor： Haim Goldberger ,  Reuven Katraro ,  Doron Gozaly

IPC: H01G4/228

CPC classification number: H01G4/228 ,  H01G4/33 ,  H01L2224/11

Abstract: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted. The standoff provides resistance to tilting.

Abstract translation: 诸如电容器的电子部件包括具有第一和第二主表面的基板，覆盖基板的第一主表面的电介质层，第一电极和第二电极。 存在覆盖第一和第二电极的钝化层，第一开口形成在第一电极上的钝化层中，第二开口形成在第二电极上的钝化层中。 第一底部电极终端位于第一开口中，而第二底部电极终端位于第二开口中。 第一底部电极端子电连接到第一电极，第二底部电极端子电连接到第二电极。 间隔件位于第一底部电极端子和第二底部电极端子之间并且附接到钝化层，从而在安装时为电子部件提供支撑。 对立提供了对倾斜的抵抗力。

公开(公告)号：US07283350B2

公开(公告)日：2007-10-16

申请号：US11293673

申请日：2005-12-02

Applicant: Reuven Katraro ,  Lilia Kushnarev ,  Nissim Cohen ,  Haim Goldberger

Inventor： Reuven Katraro ,  Lilia Kushnarev ,  Nissim Cohen ,  Haim Goldberger

IPC: H01G9/00

CPC classification number: H01G9/012 ,  H01G2/065 ,  H01G9/042 ,  H01G9/0425 ,  H01G9/08 ,  Y10T29/41 ,  Y10T29/417

Abstract: A surface mount chip capacitor includes a metal substrate, a conductive powder element including a valve metal and partially surrounding the metal substrate with the metal substrate extending outwardly from the conductive powder towards the anode end of the surface mount chip capacitor, a silver body cathode at least partially surrounding the conductive powder element, a coating formed by vapor-phase deposition surrounding the silver body cathode, an insulative material formed about a portion of the substrate extending outwardly from the conductive powder, a conductive coating formed around the metal substrate at the anode end of the surface mount chip capacitor, an end termination anode electrically connected to the conductive coating at the anode end of the surface mount chip capacitor, and an end termination cathode electrically connected to the silver body cathode at the cathode end of the surface mount chip capacitor.

Abstract translation: 表面安装片式电容器包括金属基板，包括阀金属的导电粉末元件，并部分地围绕金属基板，金属基板从导电粉末朝向表面安装片式电容器的阳极端向外延伸，银体阴极 至少部分地围绕导电粉末元件，通过围绕银体阴极的气相沉积形成的涂层，围绕从导电粉末向外延伸的部分基板形成的绝缘材料，在阳极处形成在金属基板周围的导电涂层 表面安装片式电容器的端部，与表面贴装电容器的阳极端处的导电涂层电连接的端接端子阳极，以及电连接到表面安装芯片的阴极端处的银体阴极的端部端子阴极 电容器。

公开(公告)号：US07265440B2

公开(公告)日：2007-09-04

申请号：US11125624

申请日：2005-05-10

Applicant: Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

Inventor： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Abstract translation: 一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层， 至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

公开(公告)号：US07033664B2

公开(公告)日：2006-04-25

申请号：US10277498

申请日：2002-10-22

Applicant: Gil Zilber ,  Reuven Katraro ,  Doron Teomim

Inventor： Gil Zilber ,  Reuven Katraro ,  Doron Teomim

IPC: B32B3/24 ,  B32B3/10 ,  H01L23/02

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L2224/0401 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10T428/23 ,  Y10T428/231 ,  Y10T428/239 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24562 ,  Y10T428/24661 ,  Y10T428/24744

Abstract: A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.

Abstract translation: 一种基于晶体衬底的器件，包括在其上形成有微观结构的晶体衬底和至少一个封装层，所述至少一个封装层形成在所述微结构之上，并且与所述至少一个封装层形成在所述结构衬底和所述至少一个封装层之间的至少一个间隙， 所述包装层与所述至少一个间隙连通。

公开(公告)号：US06972480B2

公开(公告)日：2005-12-06

申请号：US10462576

申请日：2003-06-16

Applicant: Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

Inventor： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC: G01R20060101 ,  H01L21/44 ,  H01L23/02 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

公开(公告)号：US5057197A

公开(公告)日：1991-10-15

申请号：US348802

申请日：1989-05-08

Applicant: Mordechai Perry ,  Reuven Katraro ,  Charles Linder

Inventor： Mordechai Perry ,  Reuven Katraro ,  Charles Linder

IPC: A23F5/16 ,  A23F5/18 ,  A23L2/74 ,  B01D61/52 ,  B01D61/58 ,  C07C51/42

CPC classification number: A23F5/16 ,  A23F5/18 ,  A23L2/74 ,  B01D61/52 ,  B01D61/58 ,  C07C51/42 ,  B01D61/025 ,  B01D61/145 ,  B01D61/147 ,  B01D61/422

Abstract: An efficient process and system for the removal of at least one organic acid from aqueous feed streams.

Abstract translation: 用于从含水进料流中除去至少一种有机酸的有效方法和系统。