公开(公告)号：US08753950B2

公开(公告)日：2014-06-17

申请号：US13432421

申请日：2012-03-28

Applicant: Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Douglas D. Coolbaugh ,  Keith E. Downes ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

公开(公告)号：US08674472B2

公开(公告)日：2014-03-18

申请号：US12853532

申请日：2010-08-10

Applicant: Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

Inventor： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

IPC: H01L21/764

CPC classification number: H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

公开(公告)号：US08338265B2

公开(公告)日：2012-12-25

申请号：US12269069

申请日：2008-11-12

Applicant: Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

Inventor： Douglas D. Coolbaugh ,  Jeffrey B. Johnson ,  Peter J. Lindgren ,  Xuefeng Liu ,  James S. Nakos ,  Bradley A. Orner ,  Robert M. Rassel ,  David C. Sheridan

IPC: H01L21/76

CPC classification number: H01L21/743 ,  H01L21/28518 ,  H01L21/76224 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.

Abstract translation: 沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。 沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。 沟槽随后填充有中间线（MOL）电介质。 可以在沟槽接触硅化物上形成接触通孔。 沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

公开(公告)号：US20120190164A1

公开(公告)日：2012-07-26

申请号：US13432421

申请日：2012-03-28

Applicant: Douglas D. COOLBAUGH ,  Keith E. DOWNES ,  Peter J. LINDGREN ,  Anthony K. STAMPER

Inventor： Douglas D. COOLBAUGH ,  Keith E. DOWNES ,  Peter J. LINDGREN ,  Anthony K. STAMPER

IPC: H01L21/02

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。 该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

公开(公告)号：US20120061801A1

公开(公告)日：2012-03-15

申请号：US13302168

申请日：2011-11-22

Applicant: David S. COLLINS ,  Kai D. FENG ,  Zhong-Xiang HE ,  Peter J. LINDGREN ,  Robert M. RASSEL

Inventor： David S. COLLINS ,  Kai D. FENG ,  Zhong-Xiang HE ,  Peter J. LINDGREN ,  Robert M. RASSEL

IPC: H01L29/92

CPC classification number: H01L29/945 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.

Abstract translation: 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。

公开(公告)号：US08125013B2

公开(公告)日：2012-02-28

申请号：US12191385

申请日：2008-08-14

Applicant: David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

Inventor： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang Ile ,  Peter J. Lindgren ,  Robert M. Rassel

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L29/945

Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.

Abstract translation: 半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。

公开(公告)号：US07859114B2

公开(公告)日：2010-12-28

申请号：US12181467

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/06 ,  H01L23/053 ,  H01L23/12

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684

Abstract: An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.

Abstract translation: 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

公开(公告)号：US20100029075A1

公开(公告)日：2010-02-04

申请号：US12181359

申请日：2008-07-29

Applicant: Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract translation: 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

公开(公告)号：US06797610B1

公开(公告)日：2004-09-28

申请号：US10248019

申请日：2002-12-11

Applicant: Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L214763

CPC classification number: H01L21/76802

Abstract: A sublitohgraphic trench is formed in a semiconductor substrate by first forming a microtrench which is subsequently used as a mask. Filled sublithographic trenches are formed with a width corresponding to the width of the microtrenches.

Abstract translation: 通过首先形成随后用作掩模的微切口，在半导体衬底中形成子晶体学沟槽。 填充的亚光刻沟槽形成为具有对应于微锥体宽度的宽度。

公开(公告)号：US20120115303A1

公开(公告)日：2012-05-10

申请号：US13354371

申请日：2012-01-20

Applicant: Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Jeffrey P. Gambino ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L21/4763 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2221/1021 ,  H01L2221/1063

Abstract: Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.

Abstract translation: 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。