公开(公告)号：US08510702B2

公开(公告)日：2013-08-13

申请号：US13297086

申请日：2011-11-15

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： An automated system, and method of operating the same, for interactively routing interconnections in a layout of an integrated circuit. Interconnections among subchips in the integrated circuit, specified by a netlist, are displayed by the system by way of airlines. The system provides a symbolic view of the bus, showing a representative wire of the bus, such as that associated with the least-significant or most-significant bit position in the bus. The physical routing of the representative wire is interactively defined, using orthogonal wire segments in selected conductor levels. Bus properties, for example including bit pitch, wire pitch, LSB/MSB, and a direction of expansion, are associated with the routing data for each segment of the representative wire. The combination of the routing data and the bus property data enable building of the entire bus from the interactive routing of the representative wire in the symbolic view.

摘要翻译： 一种自动化系统及其操作方法，用于在集成电路的布局中交互地路由互连。 由网表指定的集成电路中的子芯片之间的互连由系统通过航空公司显示。 该系统提供总线的符号视图，显示总线的代表线，例如与总线中最不重要或最高有效位位置相关联的总线。 使用选定的导体电平中的正交线段来交互地限定代表性电线的物理布线。 总线属性（例如包括位间距，线间距，LSB / MSB和扩展方向）与代表性电线的每个段的路由数据相关联。 路由数据和总线属性数据的组合使得能够以符号视图从代表性电线的交互式路由构建整个总线。

公开(公告)号：US08193832B1

公开(公告)日：2012-06-05

申请号：US13031204

申请日：2011-02-19

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： G03C8/00 ,  H03K19/082 ,  H03K19/094

CPC分类号： G06F13/14

摘要： A system comprises a plurality of requesting agents and granting agents configured in an array of rows and a plurality of columns. Corresponding to each requesting agent is a plurality of row address decoders and column address decoders, one row decoder for each row of granting agents and one column decoder for each column of granting agents. Each row decoder receives a first subset of an address' bits from a requesting agent and generates a row output bit provided to each granting agent in the row of that row address decoder. Each column decoder receives a second subset of bits of the address and generates a column output bit provided to each granting agent in the column corresponding to such column decoder. Each granting agent logically combines the row and column output bits from row and column decoders of a requesting agent to generate a request signal for the granting agent.

摘要翻译： 系统包括以行和多列的阵列配置的多个请求代理和授权代理。 对应于每个请求代理是多个行地址解码器和列地址解码器，每行授权代理的一行解码器和每列授权代理的一列解码器。 每行解码器从请求代理接收地址“位的第一子集，并且生成提供给该行地址解码器的行中的每个授权代理的行输出位。 每个列解码器接收该地址的第二比特子集，并且生成列列输出比特，该列输出比特提供给与该列解码器对应的列中的每个授权代理。 每个授权代理逻辑地组合请求代理的行和列解码器的行和列输出位以生成授权代理的请求信号。

公开(公告)号：US07409415B2

公开(公告)日：2008-08-05

申请号：US10326515

申请日：2002-12-20

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： G06F15/00

CPC分类号： G06F9/30032

摘要： An electronic system (2001) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and an input (L) for receiving a left direction argument. The system also comprises circuitry (200) for producing a first data output having the integer number of bits by rotating the input data argument in response to the first direction argument and the second direction argument. The system also comprises circuitry for providing a modified data output (502). The circuitry for providing comprises circuitry for selecting a first set of bits from the first data output as a first portion of the modified data output and circuitry for providing a second set of bits from a source other than the first data output as a second portion of the modified data output.

摘要翻译： 一种用于操纵包括整数位的输入数据自变量（D [31：0]）的电子系统（200＆lt; 1＆lt; 1＆gt;）。 该系统包括用于接收右方向参数的输入（R）和用于接收左方向参数的输入（L）。 该系统还包括用于通过响应于第一方向参数和第二方向参数旋转输入数据自变量来产生具有整数位的第一数据输出的电路（200）。 该系统还包括用于提供经修改的数据输出（502）的电路。 用于提供的电路包括用于从第一数据输出中选择作为修改数据输出的第一部分的第一组位的电路和用于从除第一数据输出之外的源提供第二组位的电路， 修改后的数据输出。

公开(公告)号：US07315540B2

公开(公告)日：2008-01-01

申请号：US10210756

申请日：2002-07-31

申请人： Patrick W Bosshart

发明人： Patrick W Bosshart

IPC分类号： H04L12/50

CPC分类号： H04J3/1611 ,  H04Q3/52 ,  H04Q2213/13103 ,  H04Q2213/13292 ,  H04Q2213/13293

摘要： A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of like-sized data quantities. The data switching circuit further comprises a plurality of addressable memories (10x), wherein each of the plurality of addressable memories comprises a plurality of memory cells. The data switching circuit further comprises circuitry (11) for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time. Lastly, the data switching circuit further comprises reading circuitry (13, 14), coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities to output channels.

摘要翻译： 数据切换电路（10）。 数据切换电路包括用于在相同时间段内接收多个数据流（ICH 0 -ICH 127）的至少一个输入（10 >）。 每个数据流包括多个相似大小的数据量。 数据切换电路还包括多个可寻址存储器（10XX），其中多个可寻址存储器中的每一个包括多个存储器单元。 数据切换电路还包括用于在第一时间段期间由数据流提供的同一组数据量的副本写入多个可寻址存储器的每一个的电路（11）。 最后，数据切换电路还包括耦合到多个可寻址存储器中的每个相应的一个可读存储器的读取电路（13,14），用于在第二时间段内读取来自各个可寻址存储器的数量的数据量并输出读取 数据量输出通道。

公开(公告)号：US06791365B2

公开(公告)日：2004-09-14

申请号：US10307183

申请日：2002-11-29

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： H03K19094

CPC分类号： H03K19/0963 ,  H03K19/00361

摘要： A dynamic logic circuit (30). The dynamic logic circuit comprises a precharge node (30PN) to be precharged to a precharge voltage (VDD) during a precharge phase and a conditional discharge path (30L, 30DT) connected to the precharge node. The conditional discharge path is operable, during an evaluate phase, to conditionally couple the precharge node to a voltage different than the precharge voltage. The dynamic logic circuit also comprises an output (OUT3) for providing a signal in response to a state at the precharge node. Lastly, the dynamic logic circuit comprises voltage maintaining circuitry (30KT1, 30KT2), coupled to the output, for coupling the precharge voltage to the precharge node during a portion of an instance of the evaluate phase when the conditional discharge path is not enabled during the instance of the evaluate phase.

摘要翻译： 动态逻辑电路（30）。 动态逻辑电路包括在预充电阶段期间预充电到预充电电压（VDD）的预充电节点（30PN）和连接到预充电节点的条件放电路径（30L，30DT）。 条件放电路径在评估阶段期间可操作地将预充电节点有条件地耦合到不同于预充电电压的电压。 动态逻辑电路还包括用于响应于预充电节点处的状态提供信号的输出（OUT3）。 最后，动态逻辑电路包括耦合到输出端的电压维持电路（30KT1,30KT2），用于在评估阶段的实例的一部分期间将预充电电压耦合到预充电节点，当条件放电路径在 评估阶段的实例。

公开(公告)号：US06553547B1

公开(公告)日：2003-04-22

申请号：US09713416

申请日：2000-11-15

申请人： Keerthinarayan P. Heragu ,  Patrick W. Bosshart

发明人： Keerthinarayan P. Heragu ,  Patrick W. Bosshart

IPC分类号： G06F1750

CPC分类号： G01R31/3183

摘要： A method for generating charge sharing test vectors for a circuit generates a first test vector (120) and a second test vector (122). The method provides a test model (98) including a logic cell (10) and an auxiliary test circuit (100) where the auxiliary test circuit (100) includes a discharge AND gate (102) and a charge sharing AND gate (104). The method generates a first test vector (120) for the test model (98) having an input pattern to discharge nodes of the logic cell (10) and evaluate discharge AND gate (102) to a logic level 1. The method generates a second test vector (122) having an input pattern to evoke the worst charge sharing behavior for the logic cell (10) and evaluate charge sharing AND gate (104) to a logic level 1.

摘要翻译： 一种用于产生电路的电荷共享测试向量的方法产生第一测试向量（120）和第二测试向量（122）。 该方法提供包括逻辑单元（10）和辅助测试电路（100）的测试模型（98），其中辅助测试电路（100）包括放电与门（102）和电荷共享与门（104）。 该方法为具有用于排放逻辑单元（10）的节点的输入模式的测试模型（98）生成第一测试向量（120），并将放电与门（102）评估为逻辑等级1.该方法产生第二测试向量 测试向量（122）具有输入模式以唤起逻辑单元（10）的最差电荷共享行为，并且将电荷共享与门（104）评估为逻辑电平1。

公开(公告)号：US06261879B1

公开(公告)日：2001-07-17

申请号：US09330770

申请日：1999-06-11

申请人： Theodore W. Houston ,  Patrick W. Bosshart

发明人： Theodore W. Houston ,  Patrick W. Bosshart

IPC分类号： H01L2104

CPC分类号： G11C7/065 ,  G11C7/062 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/7841

摘要： An integrated circuit (SAI0) comprises a first SOI transistor (T4) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. The integrated circuit further includes a second SOI transistor (T5) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. In the integrated circuit, one of the plurality of nodes of the first SOI transistor is connected to receive a first differential input signal. Moreover, a same one of the plurality of nodes of the second SOI transistor is connected to receive a second differential input signal. Lastly, the body of the first SOI transistor is connected to the body of the second SOI transistor and the bodies of the first and second SOI transistors are connected to float.

摘要翻译： 集成电路（SAI0）包括包括多个节点的第一SOI晶体管（T4），所述多个节点包括第一源极/漏极，第二源极/漏极，用于接收电位的栅极，以使得能够在 第一源极/漏极和第二源极/漏极，以及耦合到设置在第一源极/漏极和第二源极/漏极之间的主体区域的主体端子。 集成电路还包括包括多个节点的第二SOI晶体管（T5），所述多个节点包括第一源极/漏极，第二源极/漏极，用于接收电位以使第一源极 漏极和第二源极/漏极，以及耦合到设置在第一源极/漏极和第二源极/漏极之间的主体区域的主体端子。 在集成电路中，第一SOI晶体管的多个节点之一被连接以接收第一差分输入信号。 此外，第二SOI晶体管的多个节点中的相同的一个节点被连接以接收第二差分输入信号。 最后，第一SOI晶体管的主体连接到第二SOI晶体管的主体，并且第一和第二SOI晶体管的主体被连接到浮动。

公开(公告)号：US5831451A

公开(公告)日：1998-11-03

申请号：US687800

申请日：1996-07-19

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： In a preferred logic circuit embodiment (10), there is a precharge node (14) coupled to be precharged to a precharge voltage (V.sub.DD) during a precharge phase and operable to be discharged during an evaluate phase. The circuit also includes a conditional series discharge path (22, 24, and 16) connected to the precharge node and operable to couple the precharge node to a voltage different than the precharge voltage. The conditional series discharge path includes a low threshold voltage transistor (22 or 24) having a first threshold voltage, and a high threshold voltage transistor (16) having a second threshold voltage higher in magnitude than the first threshold voltage, wherein a voltage connected to a gate of the high threshold voltage transistor is disabling during the precharge phase.

摘要翻译： 在优选的逻辑电路实施例（10）中，存在预充电节点（14），其在预充电阶段期间被耦合以预充电到预充电电压（VDD），并且可以在评估阶段期间被放电。 电路还包括连接到预充电节点并且可操作以将预充电节点耦合到不同于预充电电压的电压的条件串联放电路径（22,24和16）。 条件串联放电路径包括具有第一阈值电压的低阈值电压晶体管（22或24）和具有比第一阈值电压更高的第二阈值电压的高阈值电压晶体管（16），其中连接到 高阈值电压晶体管的栅极在预充电阶段期间禁用。

公开(公告)号：US5815697A

公开(公告)日：1998-09-29

申请号：US781570

申请日：1997-01-09

申请人： Patrick W. Bosshart ,  Jonathan H. Shiell

发明人： Patrick W. Bosshart ,  Jonathan H. Shiell

IPC分类号： G06F9/26 ,  G06F9/38 ,  G06F9/28 ,  G11C7/00

CPC分类号： G06F9/3802 ,  G06F9/267 ,  G06F9/382 ,  G06F9/3875

摘要： A processor embodiment comprises a microprogram memory circuit (12) comprising a number of separately energizable banks (14a, 14b). Each of the number of separately energizable banks is operable to concurrently output at least one microinstruction. The processor further comprises circuitry for forming a microaddress for addressing the microprogram memory. This circuitry includes circuitry (26, 28) for identifying a value of a first bit (A0) and of a second bit (A1), and the microaddress comprises the first bit, the second bit, and a plurality of main bits (20c). Further, the processor includes circuitry for selectively energizing (24, 13a, 13b) a subset of the separately energizable banks in response to the value of the first bit, and the subset is less than the number of separately energizable banks. Still further, the processor includes circuitry (16) for outputting a first set of microinstructions from the subset of the separately energizable banks. Lastly, the processor includes circuitry (18) for selecting a subset of the first set of microinstructions in response to the value of the second bit, wherein the subset is less than the number of the first set of microinstructions.

摘要翻译： 处理器实施例包括微程序存储器电路（12），其包括多个可分离的可激励的组（14a，14b）。 多个可分开激活的组中的每一个可操作以同时输出至少一个微指令。 处理器还包括用于形成用于寻址微程序存储器的微地址的电路。 该电路包括用于识别第一位（A0）和第二位（A1）的值的电路（26,28），并且微地址包括第一位，第二位和多个主位（20c） 。 此外，处理器包括用于响应于第一位的值选择性地激励（24,13a，13b）可单独激活的单元的子集的电路，并且该子集小于单独可激励的单元的数量。 此外，处理器包括用于从可单独激活的存储体的子集中输出第一组微指令的电路（16）。 最后，处理器包括用于响应于第二位的值来选择第一组微指令的子集的电路（18），其中该子集小于第一组微指令的数量。

公开(公告)号：US5604889A

公开(公告)日：1997-02-18

申请号：US259845

申请日：1994-06-15

申请人： Daniel C. Pickens ,  Patrick W. Bosshart

发明人： Daniel C. Pickens ,  Patrick W. Bosshart

IPC分类号： G06F11/26 ,  G06F12/10 ,  G06F17/50 ,  G06F12/08

CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F12/10

摘要： A memory management system for use with a logic simulator 10 for storing data in each memory that is being simulated by the logic simulator 10. The system includes memory control logic 14 coupled to a physical memory 16 which is segmented into a permanent storage area P (26), a temporary storage area T1 (24) and a second temporary storage area T2 (22). Each write request from the simulator causes memory control logic 14 to store the latest request into the T2 area (22). Prior data stored in T2 (22) are first moved to the T1 (24) or P (26) storage area where other store requests for the same and other simulated locations were stored during the same simulator time interval. In this fashion, a history of simulator write activity is stored in physical memory 16 and available for rerunning or restarting the simulator 10 at or near a prior simulator cycle.