公开(公告)号：US20060255852A1

公开(公告)日：2006-11-16

申请号：US11129240

申请日：2005-05-13

申请人： John O'Donnell ,  Michael Coln ,  Maria Marti

发明人： John O'Donnell ,  Michael Coln ,  Maria Marti

IPC分类号： H03K17/687

CPC分类号： H03K17/102 ,  H03K17/063 ,  H03K17/08142 ,  H03K17/6872

摘要： An open drain driver (7) selectively switches a MOSFET switch (MN1) which is passively held in the conducting state into the non-conducting state. The MOSFET switch (MN1) switches an AC analogue input signal on a main input terminal (3) to a main output terminal (4) and the gate of the MOSFET switch (MN1) is AC coupled by a capacitor (C1) to the drain thereof. The open drain driver (7) comprises a first MOSFET (MN2) and a second MOSFET (MN3) through which the gate of the MOSFET switch (MN1) is pulled to ground (Vss). The gate of the first MOSFET (MN2) is coupled to the supply voltage (VDD) for maintaining the first MOSFET (MN2) in the open state. A control signal is applied to the gate of the second MOSFET (MN3) for selectively operating the open drain driver (7) in the conducting state for operating the MOSFET switch (MN1) in the non-conducting state. When the second MOSFET (MN3) is in the non-conducting state, the first MOSFET (MN2) remains in the conducting state until the voltage on a coupling node (9) between the first and second MOSFETs (MN2,MN3) equals the difference between its gate voltage and its threshold voltage, at which stage, any over-voltages applied to the gate of the MOSFET switch (MN1) are divided between the first and second MOSFETs (MN2,MN3). A coupling diode (D1) coupling the coupling node (9) to the supply voltage (VDD) clamps the voltage on the coupling node (9) at the supply voltage (VDD) plus the conducting voltage of the diode (D1), in the event of the voltage on the coupling node (9) rising after the first MOSFET (MN2) has gone into the non-conducting state. The coupling node (9) may be capacitively coupled to the supply voltage (VDD) by a coupling capacitor instead of or as well as the diode (D1) for limiting the voltage on the coupling node (9).

公开(公告)号：US6141671A

公开(公告)日：2000-10-31

申请号：US653125

申请日：1996-05-24

申请人： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

发明人： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  G06F17/17

CPC分类号： H03H17/0628

摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

摘要翻译： 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。 输入数据以输入采样率写入随机存取存储器。 输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统 输出采样率。 这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

公开(公告)号：US09200968B2

公开(公告)日：2015-12-01

申请号：US13561711

申请日：2012-07-30

申请人： Michael Coln ,  Alain Valentin Guery ,  Lejun Hu

发明人： Michael Coln ,  Alain Valentin Guery ,  Lejun Hu

IPC分类号： G01K7/00 ,  G01K7/16 ,  G01K15/00 ,  G01K7/18

CPC分类号： G01K7/186 ,  G01K15/005 ,  G01K2217/00 ,  G01K2219/00

摘要： An accurate, cost-efficient temperature sensor may be integrated into an integrated circuit (IC) using common materials as the IC's interconnect metallization. The temperature sensor may include an impedance element having a length of metal made of the interconnect metal, a current source connected between a first set of contacts at opposite ends of the impedance element, and an analog-to-digital converter connected between a second set of contacts at opposite ends of the impedance element. The temperature sensor may exploits the proportional relationship between the metal's resistance and temperature to measure ambient temperature. Alternatively, such a temperature sensor may be used on disposable chemical sensors where the impedance element is made of a common metal as conductors that connect a sensor reactant to sensor contacts. In either case, because the impedance element is formed of a common metal as other interconnect, it is expected to incur low manufacturing costs.

摘要翻译： 使用普通材料作为IC的互连金属化，可将精确的，具有成本效益的温度传感器集成到集成电路（IC）中。 温度传感器可以包括具有由互连金属制成的金属长度的阻抗元件，连接在阻抗元件的相对端处的第一组触点之间的电流源和连接在第二组之间的模数转换器 的阻抗元件的相对端处的触点。 温度传感器可以利用金属电阻和温度之间的比例关系来测量环境温度。 或者，这种温度传感器可以用在一次性化学传感器上，其中阻抗元件由公共金属制成，作为将传感器反应物连接到传感器触点的导体。 在任一种情况下，由于阻抗元件由作为其他互连的公共金属形成，所以预期会导致低的制造成本。

公开(公告)号：US08837099B2

公开(公告)日：2014-09-16

申请号：US12647067

申请日：2009-12-24

申请人： Michael Coln ,  Gary Carreau ,  Yoshinori Kusuda

发明人： Michael Coln ,  Gary Carreau ,  Yoshinori Kusuda

IPC分类号： H02H9/00 ,  H01L27/02

CPC分类号： H01L27/0255

摘要： Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.

摘要翻译： 公开的实施例涉及电过载保护电路。 电过载保护电路可以包括接收参考电压的中间节点，具有相反极性的第一对钳位装置，将输入信号线钳位到中间节点，以及第二对钳位装置，每个钳位装置将中间节点夹紧到 两个参考电位之一。 电过载保护电路还可以包括连接到中间节点的滤波器以减少中间节点处的噪声。

公开(公告)号：US08824626B2

公开(公告)日：2014-09-02

申请号：US13493775

申请日：2012-06-11

申请人： Michael Coln ,  Paraic Brannick ,  Colin G. Lyden ,  Cathal Murphy

发明人： Michael Coln ,  Paraic Brannick ,  Colin G. Lyden ,  Cathal Murphy

IPC分类号： H05G1/60 ,  G06G7/18 ,  A61B6/03

CPC分类号： G06G7/186

摘要： A detector circuit can include an integrator having an amplifier, a first feedback capacitor connected between an input and output of the amplifier, one or more additional feedback capacitors connected by at least one switch between the input and output of the amplifier, and a shunt capacitor connected to the output of the amplifier. The shunt capacitor can be selected to have a capacitance value greater than that of a minimum but less than that of a maximum feedback capacitance. The detector circuit can further include a sampling circuit having a sampling capacitor connected to the output of the integrator amplifier through at least one switch, wherein the sampling capacitor is separate from the shunt capacitor. A computed tomography imaging apparatus can include the detector circuit.

摘要翻译： 检测器电路可以包括具有放大器的积分器，连接在放大器的输入和输出之间的第一反馈电容器，通过放大器的输入和输出之间的至少一个开关连接的一个或多个附加反馈电容器和分流电容器 连接到放大器的输出。 可以选择并联电容器的电容值大于最小但小于最大反馈电容的电容值。 检测器电路还可以包括采样电路，该采样电路具有通过至少一个开关连接到积分放大器的输出的采样电容器，其中采样电容器与分流电容器分离。 计算机断层成像设备可以包括检测器电路。

公开(公告)号：US08754799B2

公开(公告)日：2014-06-17

申请号：US13565082

申请日：2012-08-02

申请人： Michael Coln ,  Gary Carreau ,  Yoshinori Kusuda

发明人： Michael Coln ,  Gary Carreau ,  Yoshinori Kusuda

IPC分类号： H03M1/38 ,  H03M1/12 ,  H04N5/357

CPC分类号： H03M1/124 ,  H03M1/0682 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/468 ,  H04N5/3575

摘要： A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

摘要翻译： 用于执行相关双重采样的电路系统可以包括具有放大器的信号采样级，其具有反馈电容器和耦合到放大器的输出的一对存储电容器，以及具有一对输入的差分模数转换器（ADC） 分别耦合到信号采样级的存储电容器。 信号采样级可以从传感器设备接收复位和信号值，并且可以将这些信号的处理版本存储在相应的存储电容器上。 差分ADC可以从针对复位和信号值的处理版本执行的差分数字化操作产生表示由传感器装置捕获的信号的数字值。 以这种方式，系统可以校正由采样级的部件引入的任何信号错误。

公开(公告)号：US20130194118A1

公开(公告)日：2013-08-01

申请号：US13565082

申请日：2012-08-02

申请人： Michael COLN ,  Gary R. CARREAU ,  Yoshinori KUSUDA

发明人： Michael COLN ,  Gary R. CARREAU ,  Yoshinori KUSUDA

IPC分类号： H03M1/12

CPC分类号： H03M1/124 ,  H03M1/0682 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/468 ,  H04N5/3575

摘要： A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

摘要翻译： 用于执行相关双重采样的电路系统可以包括具有放大器的信号采样级，其具有反馈电容器和耦合到放大器的输出的一对存储电容器，以及具有一对输入的差分模数转换器（ADC） 分别耦合到信号采样级的存储电容器。 信号采样级可以从传感器设备接收复位和信号值，并且可以将这些信号的处理版本存储在相应的存储电容器上。 差分ADC可以从针对复位和信号值的处理版本执行的差分数字化操作产生表示由传感器装置捕获的信号的数字值。 以这种方式，系统可以校正由采样级的部件引入的任何信号错误。

公开(公告)号：US08441104B1

公开(公告)日：2013-05-14

申请号：US13297571

申请日：2011-11-16

申请人： Lejun Hu ,  Srivatsan Parthasarathy ,  Michael Coln ,  Javier Salcedo

发明人： Lejun Hu ,  Srivatsan Parthasarathy ,  Michael Coln ,  Javier Salcedo

IPC分类号： H01L27/02

CPC分类号： H01L29/0646 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/1446 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

公开(公告)号：US20060164279A1

公开(公告)日：2006-07-27

申请号：US11045672

申请日：2005-01-26

申请人： Robert Brewer ,  Colin Lyden ,  Michael Coln

发明人： Robert Brewer ,  Colin Lyden ,  Michael Coln

IPC分类号： H03M1/12

CPC分类号： G11C27/026 ,  G11C27/024

摘要： An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.