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    Preceding instruction address based branch prediction in a pipelined processor
    21.
    发明授权
    Preceding instruction address based branch prediction in a pipelined processor 失效
    在流水线处理器中基于指令地址的分支预测

    公开(公告)号：US4858104A

    公开(公告)日：1989-08-15

    申请号：US143547

    申请日：1988-01-13

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844

    摘要： A branch prediction for predicting, prior to executing a given branch instruction, whether the branch condition of the given branch instruction will be established, utilizes an address of an instruction that precedes the given branch instruction to access the branch prediction information for the given branch instruction from a branch prediction table.

    摘要翻译： 一种分支预测，用于在执行给定的分支指令之前，预测给定分支指令的分支条件是否将被建立，利用在给定分支指令之前的指令的地址来访问给定分支指令的分支预测信息 从分支预测表。

    Data processor
    22.
    发明申请
    Data processor 审中-公开
    数据处理器

    公开(公告)号：US20070174596A1

    公开(公告)日：2007-07-26

    申请号：US11730068

    申请日：2007-03-29

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/44

    CPC分类号： G06F9/325 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3885

    摘要： A data processor, and particularly in a data processor performing condition execution on the basis of flag information, aims at obtaining a data processor having excellent code efficiency, which can reduce branch penalty. In order to attain the aforementioned object, it is so structured that, when a first instruction decoded in a first decoder is an execution condition specifying instruction specifying the execution condition for a pair of second instructions executed in parallel, a first execution condition determination unit performs determination of the execution condition for the second instructions defined by the execution condition specifying instruction on the basis of the flag information and controls assertion/non-assertion of an execution inhibit signal on the basis of whether the execution condition defined by the execution condition specifying instruction is satisfied or not.

    摘要翻译： 数据处理器，特别是在基于标志信息执行条件执行的数据处理器中，旨在获得具有优异代码效率的数据处理器，这可以减少分支损失。 为了实现上述目的，结构是，当在第一解码器中解码的第一指令是指定并行执行的一对第二指令的执行条件的执行条件指定指令时，第一执行条件确定单元执行 基于标志信息确定由执行条件指定指令定义的第二指令的执行条件，并且基于执行条件指定指令定义的执行条件来控制执行禁止信号的断言/非断言 是否满意。

    Data processor processing a jump instruction
    25.
    发明授权
    Data processor processing a jump instruction 失效
    数据处理器处理跳转指令

    公开(公告)号：US5649145A

    公开(公告)日：1997-07-15

    申请号：US537001

    申请日：1995-09-29

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

    摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

    摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

    Data processor generating jump target address of a jump instruction in parallel with decoding of the instruction
    26.
    发明授权
    Data processor generating jump target address of a jump instruction in parallel with decoding of the instruction 失效
    数据处理器与指令的解码并行地产生跳转指令的跳转目标地址

    公开(公告)号：US5617550A

    公开(公告)日：1997-04-01

    申请号：US535871

    申请日：1995-09-29

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

    摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

    摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

    Data processor for processing branch instructions
    27.
    发明授权
    Data processor for processing branch instructions 失效
    用于处理分支指令的数据处理器

    公开(公告)号：US5453927A

    公开(公告)日：1995-09-26

    申请号：US223909

    申请日：1994-04-06

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/42

    CPC分类号： G06F9/324 ,  G06F9/322 ,  G06F9/3804

    摘要： A data processor capable of efficiently processing jump instructions including an instruction fetch unit for fetching instructions from a memory, an instruction decoding unit for decoding instructions fetched by the instruction fetch unit, an instruction executing unit for executing instructions according to the decoding result of the instructions, a PC calculation unit for holding a head address of an instruction being decoded at the instruction decoding unit, adders for selectively inputting respective values of branch displacement fields transferred from the instruction fetch unit responsive to a part of a value of an instruction code field transferred from the instruction fetch unit so as to add it to the head address of the instruction transferred from the PC calculation unit, and a JA bus for transferring the addition results to the instruction fetch unit.

    摘要翻译： 一种能够有效地处理跳转指令的数据处理器，包括用于从存储器取出指令的指令提取单元，用于解码由指令获取单元取出的指令的指令解码单元，用于根据指令的解码结果执行指令的指令执行单元 PC计算单元，用于保持在指令解码单元处正在解码的指令的头地址，加法器，用于响应于传送的指令码字段的值的一部分，有选择地输入从指令获取单元传送的分支位移字段的各个值 从指令提取单元将其添加到从PC计算单元传送的指令的头地址，以及用于将加法结果传送到指令获取单元的JA总线。

    Pipelined computer
    28.
    发明授权
    Pipelined computer 失效
    流水线电脑

    公开(公告)号：US4847753A

    公开(公告)日：1989-07-11

    申请号：US72708

    申请日：1987-07-13

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3806 ,  G06F9/3861

    摘要： A pipelined computer includes an instruction cache connected to an instruction prefetch queue for storing a target address and a target instruction, with the address of a branch instruction taken as an index, and a comparator for comparing a predicted target address stored in the instruction cache with a real target address determined upon execution of the branch instruction. When both the target addresses agree in the comparator, the decoding unit and the instruction prefetch queue continue pipeline processing without alteration.

    摘要翻译： 流水线计算机包括连接到指令预取队列的指令高速缓存，用于存储目标地址和目标指令，分支指令的地址作为索引，以及比较器，用于将存储在指令高速缓存中的预测目标地址与 在执行分支指令时确定的实际目标地址。 当目标地址在比较器中都一致时，解码单元和指令预取队列继续进行流水线处理而不改变。

    Data processor assigning the same operation code to multiple operations
    29.
    发明授权
    Data processor assigning the same operation code to multiple operations 有权
    数据处理器将相同的操作代码分配给多个操作

    公开(公告)号：US06925548B2

    公开(公告)日：2005-08-02

    申请号：US09971607

    申请日：2001-10-09

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/318 ,  G06F15/00 ,  G06F15/76

    CPC分类号： G06F9/382 ,  G06F9/30167 ,  G06F9/34 ,  G06F9/3822

    摘要： A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The data processor is a VLIW (Very Long Instruction Word) system that can execute a plurality of operations in parallel, and specify the execution sequence of the operations. It can assign a plurality of operations to the same operation code, and the operations that are executed in a second or subsequent sequence are limited to only predetermined operations among the plurality of operations.

    摘要翻译： 数据处理器可以将更多数量的操作分配给具有较短长度的指令代码，从而实现高性能，高代码效率和低成本数据处理器。 数据处理器是可并行执行多个操作的VLIW（超长指令字）系统，并指定操作的执行顺序。 它可以将多个操作分配给相同的操作代码，并且在第二或后续序列中执行的操作仅限于多个操作中的预定操作。