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29 条记录 (耗时 0.034 秒)

    Multiplexed immunohistochemical assays using molecular tags
    21.
    发明授权
    Multiplexed immunohistochemical assays using molecular tags 失效
    使用分子标签的多重免疫组织化学测定

    公开(公告)号：US07122319B2

    公开(公告)日：2006-10-17

    申请号：US10702269

    申请日：2003-11-05

    申请人： Linda Liu ,  Po-Ying Chan-Hui ,  Hrair Kirakossian ,  Sharat Singh

    发明人： Linda Liu ,  Po-Ying Chan-Hui ,  Hrair Kirakossian ,  Sharat Singh

    IPC分类号： C12Q1/68 ,  G01N33/53

    CPC分类号： G01N27/44726 ,  C12Q1/6823 ,  C12Q2521/301 ,  C12Q2527/113 ,  C12Q2537/162

    摘要： Methods and compositions are provided for detection of analytes, such as cell surface moieties, preferably in multiplexed assays, such that multiple analytes can be assayed simultaneously. The methods employ analyte binding agents which are linked to oligonucleotide labels, which labels are then used for formation of cleavage structures and generation of detectable molecular tags. Preferably, multiple tags are generated per analyte binding event.

    摘要翻译： 提供了用于检测分析物的方法和组合物，例如细胞表面部分，优选在多重测定中，使得可以同时测定多种分析物。 该方法使用与寡核苷酸标签连接的分析物结合剂，然后将该标记物用于形成切割结构和产生可检测的分子标签。 优选地，每个分析物结合事件产生多个标签。

    Internal EMI shield for an optoelectronic module
    22.
    发明申请
    Internal EMI shield for an optoelectronic module 有权
    用于光电子模块的内部EMI屏蔽

    公开(公告)号：US20050152701A1

    公开(公告)日：2005-07-14

    申请号：US11029944

    申请日：2005-01-05

    申请人： Linda Liu ,  Tom Downey ,  John Moller ,  Chris Togami

    发明人： Linda Liu ,  Tom Downey ,  John Moller ,  Chris Togami

    IPC分类号： H04B10/00 ,  H04B10/28 ,  H05K9/00

    CPC分类号： G02B6/4277 ,  G02B6/4246 ,  H04B10/43 ,  H04B10/801 ,  H05K9/0058

    摘要： A shield device for preventing the emission of electromagnetic interference (“EMI”) from an optoelectronic device, such as an optical transceiver, is disclosed. In particular, an EMI shield is disclosed for placement within an optical transceiver module in order to intercept and absorb EMI produced by electronic components included within the transceiver. This absorption by the EMI shield prevents EMI from escaping the optical transceiver module and interfering with other electronic components that are typically placed in close proximity to the transceiver. The EMI shield in one embodiment includes a sheet of EMI absorbing material that is sized for placement within the transceiver. The EMI shield can be interposed between an outer shell of the transceiver and electronic components located on a printed circuit board that is disposed within the transceiver. The proximity of the EMI shield to the EMI-producing electronic components maximizes EMI absorption by the shield.

    摘要翻译： 公开了一种用于防止来自诸如光收发器之类的光电子器件的电磁干扰（“EMI”）的发射的屏蔽装置。 特别地，公开了用于放置在光收发器模块内的EMI屏蔽，以便截取和吸收由包含在收发器内的电子元件产生的EMI。 EMI屏蔽的这种吸收防止EMI从光收发器模块中逸出，并干扰通常放置在收发器附近的其他电子元件。 EMI屏蔽在一个实施例中包括一片EMI吸收材料，其尺寸适于放置在收发器内。 EMI屏蔽可插入在收发器的外壳和位于设置在收发器内的印刷电路板上的电子元件之间。 EMI屏蔽对EMI产生电子部件的接近使屏蔽件的EMI吸收最大化。

    Method for forming an ESD protection device for antifuses with top polysilicon electrode
    28.
    发明授权
    Method for forming an ESD protection device for antifuses with top polysilicon electrode 失效
    用于形成具有顶部多晶硅电极的反熔丝的ESD保护装置的方法

    公开(公告)号：US5656534A

    公开(公告)日：1997-08-12

    申请号：US607375

    申请日：1996-02-27

    申请人： Wenn-Jei Chen ,  Huan-Chung Tseng ,  Yeouchung Yen ,  Linda Liu

    发明人： Wenn-Jei Chen ,  Huan-Chung Tseng ,  Yeouchung Yen ,  Linda Liu

    IPC分类号： H01L23/525 ,  H01L23/60 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L23/5252 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/954

    摘要： The present invention is directed to providing an electrostatic discharge ("ESD") protection cell for use in an integrated circuit device including antifuses. The ESD protection cell is formed simultaneously with the antifuses that it protects and provides protection from ESD during the fabrication of the antifuses. The concept is to use thin undoped or doped polysilicon on top of antifuse material as a block etching mask for the formation of the ESD protection cells by using common etching techniques. This polysilicon mask is placed where the antifuses will be and not where the ESD protection cells will be. The polysilicon mask is then merged with a top polysilicon electrode during later processing. During the block etching process, the antifuse material layer is compromised in the region about the ESD protection cells. Where the antifuse material layer is an O--N--O sandwich, the top oxide and nitride layers may be etching during the block etching process leaving the thin bottom oxide layer and some or no residual bottom oxide of the ONO composite antifuse material layer for forming the ESD protection cell. Since etching into the bottom oxide of the ONO composite antifuse material layer will not degrade, but will enhance the ESD protection capability of the ESD protection cell, it is perfectly acceptable to also etch the bottom oxide layer as well as long as proper process control is allowed. The ESD protection cell may be used with antifuses having diffusion or polysilicon type bottom electrodes and polysilicon top electrodes. An advantage of this structure is its ability to be fabricated at high temperature for improved film characteristics and reliability.

    摘要翻译： 本发明旨在提供一种用于包括反熔丝的集成电路装置中的静电放电（“ESD”）保护电池。 ESD保护电池与其保护的反熔丝同时形成，并且在制造抗反熔丝期间提供防止ESD的保护。 该概念是在反熔丝材料的顶部上使用薄的未掺杂或掺杂的多晶硅作为用于通过使用常规蚀刻技术形成ESD保护电池的块蚀刻掩模。 将该多晶硅掩模放置在反熔丝将会存在的地方，而不是ESD保护电池的地方。 然后在后续处理期间将多晶硅掩模与顶部多晶硅电极合并。 在块蚀刻工艺期间，反熔丝材料层在围绕ESD保护电池的区域中受损。 当反熔丝材料层为ONO夹层时，顶部氧化物层和氮化物层可以在块蚀刻工艺期间进行蚀刻，留下薄的底部氧化物层和用于形成ESD保护电极的ONO复合反熔丝材料层的一些或不存在底部氧化物 。 由于蚀刻到ONO复合反熔体材料层的底部氧化物不会降解，而是将增强ESD保护电池的ESD保护能力，所以也可以蚀刻底部氧化物层，以及正确的过程控制是 允许 ESD保护电池可以与具有扩散或多晶硅型底电极和多晶硅顶电极的反熔丝一起使用。 该结构的优点是其在高温下制造以提高膜特性和可靠性的能力。

    ESD protection device for antifuses with top polysilicon electrode
    29.
    发明授权
    ESD protection device for antifuses with top polysilicon electrode 失效
    具有顶部多晶硅电极的反熔丝的ESD保护装置

    公开(公告)号：US5572061A

    公开(公告)日：1996-11-05

    申请号：US289678

    申请日：1994-08-12

    申请人： Wenn-Jei Chen ,  Huan-Chung Tseng ,  Yeouchung Yen ,  Linda Liu

    发明人： Wenn-Jei Chen ,  Huan-Chung Tseng ,  Yeouchung Yen ,  Linda Liu

    IPC分类号： H01L23/525 ,  H01L23/60 ,  H01L29/00 ,  H01L23/48

    CPC分类号： H01L23/5252 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/954

    摘要： The present invention is directed to providing an electrostatic discharge ("ESD") protection cell for use in an integrated circuit device including antifuses. The ESD protection cell is formed simultaneously with the antifuses that it protects and provides protection from ESD during the fabrication of the antifuses. The concept is to use thin undoped or doped polysilicon on top of antifuse material as a block etching mask for the formation of the ESD protection cells by using common etching techniques. This polysilicon mask is placed where the antifuses will be and not where the ESD protection cells will be. The polysilicon mask is then merged with a top polysilicon electrode during later processing. During the block etching process, the antifuse material layer is compromised in the region about the ESD protection cells. Where the antifuse material layer is an O--N--O sandwich, the top oxide and nitride layers may be etching during the block etching process leaving the thin bottom oxide layer and some or no residual bottom oxide of the ONO composite antifuse material layer for forming the ESD protection cell. Since etching into the bottom oxide of the ONO composite antifuse material layer will not degrade, but will enhance the ESD protection capability of the ESD protection cell, it is perfectly acceptable to also etch the bottom oxide layer as well as long as proper process control is allowed. The ESD protection cell may be used with antifuses having diffusion or polysilicon type bottom electrodes and polysilicon top electrodes. An advantage of this structure is its ability to be fabricated at high temperature for improved film characteristics and reliability.

    摘要翻译： 本发明旨在提供一种用于包括反熔丝的集成电路装置中的静电放电（“ESD”）保护电池。 ESD保护电池与其保护的反熔丝同时形成，并且在制造抗反熔丝期间提供防止ESD的保护。 该概念是在反熔丝材料的顶部上使用薄的未掺杂或掺杂的多晶硅作为用于通过使用常规蚀刻技术形成ESD保护电池的块蚀刻掩模。 将该多晶硅掩模放置在反熔丝将会存在的地方，而不是ESD保护电池的地方。 然后在后续处理期间将多晶硅掩模与顶部多晶硅电极合并。 在块蚀刻工艺期间，反熔丝材料层在围绕ESD保护电池的区域中受损。 当反熔丝材料层为ONO夹层时，顶部氧化物层和氮化物层可以在块蚀刻工艺期间进行蚀刻，留下薄的底部氧化物层和用于形成ESD保护电极的ONO复合反熔丝材料层的一些或不存在底部氧化物 。 由于蚀刻到ONO复合反熔体材料层的底部氧化物不会降解，而是将增强ESD保护电池的ESD保护能力，所以也可以蚀刻底部氧化物层，以及正确的过程控制是 允许 ESD保护电池可以与具有扩散或多晶硅型底电极和多晶硅顶电极的反熔丝一起使用。 该结构的优点是其在高温下制造以提高膜特性和可靠性的能力。