公开(公告)号：US06611028B2

公开(公告)日：2003-08-26

申请号：US10266661

申请日：2002-10-08

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

公开(公告)号：US06582981B2

公开(公告)日：2003-06-24

申请号：US09904138

申请日：2001-07-13

Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

IPC: H01L3118

CPC classification number: H01L31/0352 ,  H01L31/102 ,  Y10S438/979

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

公开(公告)号：US06362491B1

公开(公告)日：2002-03-26

申请号：US09409876

申请日：1999-10-01

Applicant: Jen-Pan Wang ,  Lin-June Wu

Inventor： Jen-Pan Wang ,  Lin-June Wu

IPC: G01B1100

CPC classification number: G03F7/70633 ,  G03F7/70475

Abstract: A method of determining overlay accuracy, using visual inspection, of a first circuit pattern relative to a second circuit pattern. The first circuit pattern and the second circuit pattern are too large to be contained in a single reticle and are formed separately on an integrated circuit wafer and photo stitched together. A first overlay pattern is located adjacent to the first circuit pattern on a mask. A second overlay pattern is located adjacent to the second circuit pattern on a mask, preferably, but not necessarily, the same mask. The first overlay pattern and the second overlay pattern are located so that their images in the layer of developed photoresist will be adjacent to each other after the photoresist is exposed with the first and second circuit patterns and developed. Visual observation of the images of the first and second overlay patterns is then used to determine the overlay accuracy of the first circuit pattern relative to the second circuit pattern.

Abstract translation: 使用目视检查相对于第二电路图案的第一电路图案的覆盖精度的方法。 第一电路图案和第二电路图案太大而不能包含在单个掩模版中，并且分别形成在集成电路晶片上并且被照相缝合在一起。 第一覆盖图案位于与掩模上的第一电路图案相邻的位置。 第二覆盖图案位于掩模附近的第二电路图案附近，优选但不一定是相同的掩模。 第一覆盖图案和第二覆盖图案被定位成使得它们在显影的光致抗蚀剂层中的图像将在用第一和第二电路图案曝光光致抗蚀剂并显影之后彼此相邻。 然后使用第一和第二覆盖图案的图像的视觉观察来确定第一电路图案相对于第二电路图案的覆盖精度。

公开(公告)号：US06329717B1

公开(公告)日：2001-12-11

申请号：US08616140

申请日：1996-03-14

Applicant: Syun-Ming Jang ,  Chen-Hua Yu ,  Lung Chen ,  Lin-June Wu

Inventor： Syun-Ming Jang ,  Chen-Hua Yu ,  Lung Chen ,  Lin-June Wu

IPC: H01L2348

CPC classification number: H01L21/76801

Abstract: A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate as the silicon source material. The silicon oxide insulator spacer layer is formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.

Abstract translation: 一种用于在集成电路内的多层图案化金属堆叠之间选择性地沉积氧化硅绝缘体间隔层的方法。 形成在半导体衬底上的是通过等离子体增强化学气相沉积（PECVD）工艺形成的氧化硅绝缘体衬底层。 在氧化硅绝缘体衬底层形成多层图案化的金属叠层时。 多层图案化的金属堆叠具有由氮化钛形成的顶部阻挡金属层和由含铝合金形成的下部导体金属层。 在通过多层图案化的金属堆叠暴露的氧化硅绝缘体基底层的部分上并且通过多层图案化的金属堆叠暴露的含铝合金的边缘上选择性地形成氧化硅绝缘体间隔层。 氧化硅绝缘体间隔层通过使用四乙基正硅酸盐作为硅源材料的臭氧辅助化学气相沉积（CVD）工艺形成。 形成氧化硅绝缘体间隔层，用于在由氮化钛形成的顶部阻挡金属层上形成氧化硅绝缘体间隔层的沉积时间不超过孵育时间。

公开(公告)号：US5747381A

公开(公告)日：1998-05-05

申请号：US599770

申请日：1996-02-12

Applicant: Lin-June Wu ,  Chen-Hua Douglas Yu ,  Jin-Yuan Lee

Inventor： Lin-June Wu ,  Chen-Hua Douglas Yu ,  Jin-Yuan Lee

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/31133 ,  H01L21/76801 ,  H01L21/76819 ,  H01L2924/0002

Abstract: This invention relates to a method for removing residual spin-on-glass (SOG) during a planarization processing step wherein the SOG is used as a sacrificial planarization medium and subjected to a full etchback to an underlying interlevel dielectric (ILD) layer. The SOG is applied over the ILD layer, and etched back into the ILD layer by reactive-ion-etching under conditions of comparable etch rates for both SOG and ILD. At endpoint there some residual pockets of SOG can be present as well as a region of SOG along the edges of the wafer where it is clamped in the etchback tool. The residual SOG must be removed completely to avoid SOG cracking after thermal processing and SOG outgassing during subsequent metal deposition. For this purpose an aqueous etch consisting of hydrofluoric acid buffered with ammonium fluoride is used. The etchant composition chosen exhibits a selectivity for SOG over the ILD glass of greater than 40 making it suitable for removing considerable SOG residues with minimal attack of the ILD.

Abstract translation: 本发明涉及一种用于在平坦化处理步骤期间去除残留旋涂玻璃（SOG）的方法，其中SOG用作牺牲平坦化介质并经受完全回蚀至下层层间电介质（ILD）层。 将SOG施加在ILD层上，并通过反应离子蚀刻在SOG和ILD的相当的蚀刻速率条件下回蚀入ILD层。 在端点，可以存在一些残留的SOG袋，以及沿着晶片边缘的SOG区域，其中它被夹在回蚀工具中。 残留的SOG必须完全去除，以避免后续金属沉积过程中热处理后的SOG开裂和SOG脱气。 为此，使用由氟化氢缓冲的氢氟酸组成的水性蚀刻。 所选择的蚀刻剂组合物显示对超过40的ILD玻璃的SOG选择性，使其适合于以最小的ILD攻击去除相当大的SOG残留物。

公开(公告)号：US5518959A

公开(公告)日：1996-05-21

申请号：US518706

申请日：1995-08-24

Applicant: Syun-Ming Jang ,  Chen-Hua Yu ,  Lung Chen ,  Lin-June Wu

Inventor： Syun-Ming Jang ,  Chen-Hua Yu ,  Lung Chen ,  Lin-June Wu

IPC: H01L21/768 ,  H01L21/283

CPC classification number: H01L21/76801

Abstract: A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate as the silicon source material. The silicon oxide insulator spacer layer is formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.

Abstract translation: 一种用于在集成电路内的多层图案化金属堆叠之间选择性地沉积氧化硅绝缘体间隔层的方法。 形成在半导体衬底上的是通过等离子体增强化学气相沉积（PECVD）工艺形成的氧化硅绝缘体衬底层。 在氧化硅绝缘体衬底层形成多层图案化金属叠层时。 多层图案化的金属堆叠具有由氮化钛形成的顶部阻挡金属层和由含铝合金形成的下部导体金属层。 在通过多层图案化的金属堆叠暴露的氧化硅绝缘体基底层的部分上并且通过多层图案化的金属堆叠暴露的含铝合金的边缘上选择性地形成氧化硅绝缘体隔离层。 氧化硅绝缘体间隔层通过使用四乙基正硅酸盐作为硅源材料的臭氧辅助化学气相沉积（CVD）工艺形成。 形成氧化硅绝缘体间隔层，用于在由氮化钛形成的顶部阻挡金属层上形成氧化硅绝缘体间隔层的沉积时间不超过孵育时间。

公开(公告)号：US20050277262A1

公开(公告)日：2005-12-15

申请号：US10867336

申请日：2004-06-14

Applicant: Chang-Sheng Tsao ,  Jung-Hui Kao ,  Yen-Ming Chen ,  Lin-June Wu

Inventor： Chang-Sheng Tsao ,  Jung-Hui Kao ,  Yen-Ming Chen ,  Lin-June Wu

IPC: H01L21/76 ,  H01L21/762

CPC classification number: C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  H01L21/31053 ,  H01L21/76243

Abstract: A method for manufacturing isolation structures in a semiconductor device includes providing a substrate with a surface. A plurality of ions are implanted below the surface of the substrate and the substrate is then annealed to form a layer below its surface. Isolation structures may then be formed in the substrate extending from the surface of the substrate to approximately the depth of the layer.

Abstract translation: 一种用于制造半导体器件中的隔离结构的方法包括：提供具有表面的衬底。 将多个离子注入到衬底的表面下方，然后将衬底退火以在其表面下形成一层。 然后可以在从衬底的表面延伸到衬底的深度的衬底中形成隔离结构。

公开(公告)号：US06468904B1

公开(公告)日：2002-10-22

申请号：US09883162

申请日：2001-06-18

Applicant: Dian-Hau Chen ,  Fu-Mei Chiu ,  Lin-June Wu

Inventor： Dian-Hau Chen ,  Fu-Mei Chiu ,  Lin-June Wu

IPC: H01L2144

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/4933

Abstract: A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas wherein at least one device area is to be silicided and wherein at least one device area is not to be silicided. A composite resist protective oxide layer is formed overlying device areas comprising a first layer of oxide and a second layer of silicon oxynitride. The silicon oxynitride layer is dry etched away overlying the device area to be silicided. Thereafter, the oxide layer is wet etched away overlying the device area to be silicided. Silicidation is performed to complete fabrication of the integrated circuit device.

Abstract translation: 描述了在制造集成电路中的自对准硅化物工艺中通过使用复合层和两步蚀刻工艺形成改进的RPO层的方法。 在半导体衬底上形成隔离区域，该半导体衬底围绕并电绝缘器件区域，其中至少一个器件区域将被硅化，并且其中至少一个器件区域不被硅化。 复合抗蚀剂保护氧化物层形成在包括第一氧化物层和氮氧化硅第二层的器件区域上。 将氮氧化硅层干式蚀刻掉，覆盖要被硅化的器件区域。 此后，将氧化物层湿式蚀刻掉，覆盖要被硅化的器件区域。 执行硅化以完成集成电路器件的制造。

公开(公告)号：US06465308B1

公开(公告)日：2002-10-15

申请号：US09863222

申请日：2001-05-24

Applicant: Tao Cheng ,  Jyh-Cheng You ,  Lin-June Wu

Inventor： Tao Cheng ,  Jyh-Cheng You ,  Lin-June Wu

IPC: H01L21336

CPC classification number: H01L29/66613 ,  H01L27/0266

Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element. The gate and drain of the thick oxide FET device are connected to the input/output connection pad of the internal semiconductor circuits which also enhances ESD protection. The FET source element is connected to another voltage source, typically ground, providing a path to shunt the current from an ESD incident thereby protecting the internal circuitry from damage.

Abstract translation: 描述了用于制造具有改进的用于高电压应用的ESD保护的半导体器件的结构和工艺。 在内部有源电路的输入/输出处开发出具有可调阈值电压（Vt）的厚栅极氧化物N沟道场效应晶体管（FET）器件，用于为9伏及更高范围内的应用提供ESD保护 。 FET阈值电压决定ESD保护特性。 使用N场注入来提供厚氧化物栅极元件下方的掺杂剂区域，该掺杂剂区域具有改变该器件的阈值电压（Vt）的效果，使得器件导通被“调谐”以更紧密地匹配应用 内部半导体电路的要求。 通过使用金属栅极电极或多晶硅栅极元件来完成栅极电接触。 厚氧化物FET器件的栅极和漏极连接到内部半导体电路的输入/输出连接焊盘，这也增强了ESD保护。 FET源极元件连接到通常为接地的另一个电压源，提供了从ESD入射分流电流的路径，从而保护内部电路免受损坏。

公开(公告)号：US06297102B1

公开(公告)日：2001-10-02

申请号：US09409874

申请日：1999-10-01

Applicant: Jyh-Cheng You ,  Lin-June Wu

Inventor： Jyh-Cheng You ,  Lin-June Wu

IPC: H01L218234

CPC classification number: H01L27/118 ,  H01L21/823807 ,  H01L21/823814

Abstract: The invention provides a method for forming a ROM cell surface implant region using a PLDD implant. A semiconductor structure is provided comprising a substrate having isolation structures thereon, which separate and electrically isolating a first area having a P-well formed in the substrate and a gate over the substrate, a second area having a N-well formed in the substrate and a gate over the substrate, and a third area having P-well and buried N+ regions formed in the substrate with second isolation structures overlying the buried N+ regions. A photoresist mask is formed exposing the first area, and impurity ions are implanted to form n-type lightly doped source and drain regions. The photoresist mask is removed and a new (PLDD/ROM) photoresist mask is formed exposing the second area and the third area. Impurity ions are implanted to simultaneously form p-type lightly doped source and drain regions and a ROM cell surface implant region region. The PLDD/ROM photoresist mask is then removed.

Abstract translation: 本发明提供了一种使用PLDD植入物形成ROM细胞表面植入区域的方法。 提供了一种半导体结构，包括其上具有隔离结构的衬底，其分离并电绝缘在衬底中形成的P阱的第一区域和衬底上的栅极，在衬底中形成有N阱的第二区域， 在衬底上方的栅极，以及在衬底中形成有P阱和掩埋N +区的第三区，其中第二隔离结构覆盖在掩埋的N +区上。 形成曝光第一区域的光致抗蚀剂掩模，并且注入杂质离子以形成n型轻掺杂的源极和漏极区域。 除去光致抗蚀剂掩模，并形成暴露第二区域和第三区域的新的（PLDD / ROM）光致抗蚀剂掩模。 植入杂质离子以同时形成p型轻掺杂源极和漏极区域以及ROM单元表面注入区域。 然后去除PLDD / ROM光刻胶掩模。