公开(公告)号：US5983332A

公开(公告)日：1999-11-09

申请号：US672982

申请日：1996-07-01

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F13/36 ,  G06F12/10 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04L49/309 ,  G06F12/1027 ,  G06F12/1081 ,  H04L45/7453 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652

摘要： An apparatus and method for translating a virtual address to a physical address utilizing an address translation unit implemented within a network interface card is described. The address translation unit of the present invention is utilized in a computer system. The computer system comprises a first bus; processors with embedded caches and memory coupled to the first bus; a second bus; a network logic coupled to the second bus, wherein the network logic includes an address translation unit; and a bus bridge coupled to the first bus and to the second bus.

摘要翻译： 描述了利用在网络接口卡内实现的地址转换单元将虚拟地址转换为物理地址的装置和方法。 本发明的地址转换单元用于计算机系统中。 计算机系统包括第一总线; 具有嵌入式高速缓存和存储器的处理器耦合到第一总线; 第二班车 耦合到所述第二总线的网络逻辑，其中所述网络逻辑包括地址转换单元; 以及耦合到第一总线和第二总线的总线桥。

公开(公告)号：US5675811A

公开(公告)日：1997-10-07

申请号：US516850

申请日：1995-08-18

申请人： Walter F. Broedner ,  Anthony M. Fadell ,  Stephen G. Perlman ,  John E. Watkins

发明人： Walter F. Broedner ,  Anthony M. Fadell ,  Stephen G. Perlman ,  John E. Watkins

IPC分类号： G06F13/42 ,  G06F11/30

CPC分类号： G06F13/4291

摘要： A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch in a base station (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Data and commands are sent from the base station to a peripheral device, and data is received from the peripheral device by the base station by configuring each peripheral device on the bus to receive data and clock signals from the base station in an idle mode of operation. Upon a command send being transmitted by the base station, all peripheral devices on the serial bus between the base station and an addressed peripheral device remain in the idle mode and the addressed peripheral device is connected to the bus so that clock and data signals on the bus to are passed to the peripheral device. When the peripheral devices on the bus are in the idle mode of operation, and the base station transmits a command get to an addressed peripheral device, the addressed peripheral device and all peripheral devices between the addressed peripheral device and the base station are reconfigured to transmit clock and data signals from the addressed peripheral device to the base station.

摘要翻译： 低功耗，单主机，可变时钟速率，菊花链式串行总线将基站（主站）中的总线调度连接到一个或多个菊花链外围设备（从站）的链路。 总线具有双向串行数据线，双向时钟线，单向中断线，电源线和接地线。 数据和命令从基站发送到外围设备，并且基站通过配置总线上的每个外围设备从外围设备接收数据，以在空闲操作模式下从基站接收数据和时钟信号 。 当基站发送的命令发送时，基站和寻址的外围设备之间的串行总线上的所有外围设备保持在空闲模式，并且所寻址的外围设备连接到总线，使得时钟和数据信号在 总线传递到外围设备。 当总线上的外围设备处于空闲操作模式时，并且基站向寻址的外围设备发送命令，寻址的外围设备和所寻址的外围设备与基站之间的所有外围设备被重新配置为传送 时钟和数据信号从寻址的外围设备到基站。

公开(公告)号：US08458368B2

公开(公告)日：2013-06-04

申请号：US12471637

申请日：2009-05-26

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F12/00 ,  G06F9/46

CPC分类号： G06F9/5011

摘要： A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

摘要翻译： 系统包括耦合到一个或多个处理单元的虚拟化I / O设备。 虚拟化I / O设备包括对应于硬件资源的编程I / O（PIO）配置寄存器和用于存储包括多个条目的资源表的存储器。 每个条目对应于相应的硬件资源。 系统处理器可以将硬件资源分配给可以包括物理和虚拟功能的功能，并且可以使用指示所请求的硬件资源是否已被分配给请求进程的编码值来编程每个功能的资源发现表的每个条目， 以及请求的硬件资源是否与另一个功能共享。 处理单元可以执行与给定进程相关联的设备驱动器实例，以通过请求对资源发现表的访问来发现分配的资源。 虚拟化I / O设备通过检查对资源发现表的访问请求来保护资源。

公开(公告)号：US08402320B2

公开(公告)日：2013-03-19

申请号：US12786988

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F11/00

CPC分类号： G06F11/0766 ,  G06F11/0724 ,  G06F11/0745

摘要： An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

摘要翻译： I / O设备包括主机接口，其可以被配置为接收和处理由多个处理单元发送的多个事务分组，每个处理单元对应于相应的根复合体。 主机接口包括错误处理单元，其具有在硬件中实现的错误逻辑，其可被配置为确定每个事务包是否具有错误并存储与存储器内的任何检测到的错误相对应的信息。 更具体地，错误处理单元可以在事件包被接收或实时地执行错误检测和捕获错误信息，而错误处理单元可以包括可以随后处理与检测到的错误相对应的信息的固件。

公开(公告)号：US08312461B2

公开(公告)日：2012-11-13

申请号：US12135356

申请日：2008-06-09

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F3/00 ,  G06F12/02 ,  G06F13/14 ,  G06F12/00 ,  G06F13/16 ,  G06F12/06

CPC分类号： G06F13/12 ,  G06F12/1441

摘要： A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

摘要翻译： 系统包括耦合到一个或多个处理单元的虚拟化I / O设备。 虚拟化I / O设备包括用于存储资源发现表的存储器和对应于硬件资源的编程I / O（PIO）配置寄存器。 系统处理器可以将多个硬件资源分配给一个或多个功能，并且为每个功能填充资源发现表的每个条目。 处理单元可以执行一个或多个处理。 给定的处理单元可以进一步执行OS指令以为系统存储器中的PIO配置空间的I / O映射分配空间，并且将功能分配给相应的进程。 处理单元可以执行与给定进程相关联的设备驱动器实例，以通过请求对资源发现表的访问来发现分配的资源。 虚拟化I / O设备通过检查对资源发现表的访问请求来保护资源。

公开(公告)号：US08117350B2

公开(公告)日：2012-02-14

申请号：US12611694

申请日：2009-11-03

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F3/00

CPC分类号： G06F13/4221

摘要： The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

摘要翻译： 所描述的实施例提供用于访问配置空间寄存器（CSR）的值的系统。 该系统包括具有地址输入和CSR数据输出的CSR数据存储机制。 CSR数据存储机制包括存储多个存储器位置的存储器，用于存储针对相应设备的功能的CSR的真实值或实际值。 在这些实施例中，存储器位置被划分为至少一个共享区域和至少一个唯一区域。 在这些实施例中，响应于接收地址输入上的存储器位置的地址，CSR数据存储机构访问对应共享区域或唯一区域中的存储器位置中的CSR值。

公开(公告)号：US20110296255A1

公开(公告)日：2011-12-01

申请号：US12786988

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F11/07

CPC分类号： G06F11/0766 ,  G06F11/0724 ,  G06F11/0745

摘要： An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

摘要翻译： I / O设备包括主机接口，其可以被配置为接收和处理由多个处理单元发送的多个事务分组，每个处理单元对应于相应的根复合体。 主机接口包括错误处理单元，其具有在硬件中实现的错误逻辑，其可被配置为确定每个事务包是否具有错误并存储与存储器内的任何检测到的错误相对应的信息。 更具体地，错误处理单元可以在事件包被接收或实时地执行错误检测和捕获错误信息，而错误处理单元可以包括可以随后处理与检测到的错误相对应的信息的固件。

公开(公告)号：US20100306416A1

公开(公告)日：2010-12-02

申请号：US12471637

申请日：2009-05-26

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F3/00 ,  G06F12/02 ,  G06F13/14 ,  G06F12/00 ,  G06F13/16 ,  G06F12/06

CPC分类号： G06F9/5011

摘要： A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

摘要翻译： 系统包括耦合到一个或多个处理单元的虚拟化I / O设备。 虚拟化I / O设备包括对应于硬件资源的编程I / O（PIO）配置寄存器和用于存储包括多个条目的资源表的存储器。 每个条目对应于相应的硬件资源。 系统处理器可以将硬件资源分配给可以包括物理和虚拟功能的功能，并且可以使用指示所请求的硬件资源是否已被分配给请求进程的编码值来编程每个功能的资源发现表的每个条目， 以及请求的硬件资源是否与另一个功能共享。 处理单元可以执行与给定进程相关联的设备驱动器实例，以通过请求对资源发现表的访问来发现分配的资源。 虚拟化I / O设备通过检查对资源发现表的访问请求来保护资源。

公开(公告)号：US07836328B1

公开(公告)日：2010-11-16

申请号：US11418900

申请日：2006-05-04

申请人： Rahoul Puri ,  John E. Watkins ,  Arvind Srinivsan ,  Babu R. Kandimalla ,  Nimita Taneja

发明人： Rahoul Puri ,  John E. Watkins ,  Arvind Srinivsan ,  Babu R. Kandimalla ,  Nimita Taneja

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0745

摘要： A method and apparatus for recovering from errors occurring during system bus transactions. An input/output device such as a network interface unit (NIU) issues read and write operations across a meta interface coupling the device to host bus (glue) logic. The host bus logic translates the operations into system bus transactions. The device maintains a set of reusable identifiers for identifying the operations, and a table maintained by the device or the host bus logic maps the operation identifiers to transaction identifiers identifying the system bus transactions spawned to perform the operations. If a bus transaction encounters an unrecoverable error, the host bus logic reports the error to the device and drops any further data received from other bus transactions performed for the same operation. The device marks the operation's identifier as dirty, to prevent its reuse. The operation identifier may be reused after software clears the error condition.

摘要翻译： 一种用于从系统总线事务期间发生的错误中恢复的方法和装置。 诸如网络接口单元（NIU）的输入/输出设备通过将设备耦合到主机总线（胶合）逻辑的元接口发出读取和写入操作。 主机总线逻辑将操作转换为系统总线事务。 设备维护一组用于识别操作的可重用标识符，并且由设备或主机总线逻辑维护的表将操作标识符映射到识别为执行操作而产生的系统总线事务的事务标识符。 如果总线事务遇到不可恢复的错误，则主机总线逻辑将错误报告给设备，并丢弃从为相同操作执行的其他总线事务接收到的任何其他数据。 设备将操作的标识符标记为脏，以防止其重复使用。 在软件清除错误状态之后，可以重新使用操作标识符。

公开(公告)号：US07124319B2

公开(公告)日：2006-10-17

申请号：US10389444

申请日：2003-03-14

申请人： John E. Watkins ,  Paul J. Garnett ,  Stephen Rowlinson

发明人： John E. Watkins ,  Paul J. Garnett ,  Stephen Rowlinson

IPC分类号： G06F11/00

CPC分类号： H04L1/22

摘要： A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are joined by a bridge, and there is a communications link for each processing set for transmitting data from the processing set to the bridge. Data transmissions are initiated in synchronism with one another from the respective processing sets to the bridge but are then subject to variable delay over the communications link. Accordingly, a buffer is included in the bridge for storing the data transmissions received from the processing sets for long enough to compensate for the variable delay. The data transmissions can then be fed out from the buffer to a comparator that verifies that the data transmissions received from the two or more processing sets properly match each other. Likewise, a buffer is included in each processing set for storing the data transmissions received from the bridge for long enough to compensate for the variable delay. Control logic in each processing set can then apply the data transmissions to the respective processing set at a predetermined time.

摘要翻译： 提供了容错计算系统，其包括彼此同步地操作的两个或多个处理集合。 两个处理集合通过桥连接，并且存在用于将数据从处理集传送到网桥的每个处理集合的通信链路。 数据传输从相应的处理集合到桥接器彼此同步发起，然后在通信链路上经受可变延迟。 因此，桥接器中包括缓冲器，用于存储从处理集合接收的数据传输足够长以补偿可变延迟。 然后可以将数据传输从缓冲器馈送到比较器，该比较器验证从两个或更多个处理集合接收的数据传输是否正确匹配。 同样地，每个处理集合中包括缓冲器，用于存储从桥接器接收的数据传输足够长以补偿可变延迟。 然后，每个处理集合中的控制逻辑可以在预定时间将数据传输应用于各个处理集合。