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50 条记录 (耗时 0.016 秒)

    JFET structure for integrated circuit and fabrication method
    21.
    发明授权
    JFET structure for integrated circuit and fabrication method 有权
    集成电路和制造方法的JFET结构

    公开(公告)号：US06861303B2

    公开(公告)日：2005-03-01

    申请号：US10434642

    申请日：2003-05-09

    申请人： Pinghai Hao ,  Fan-Chi Hou ,  Imran Khan

    发明人： Pinghai Hao ,  Fan-Chi Hou ,  Imran Khan

    IPC分类号： H01L21/337 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/80 ,  H01L29/808

    CPC分类号： H01L27/085 ,  G11C2211/4068 ,  H01L21/8232 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

    摘要： Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.

    摘要翻译： 结型场效应晶体管（JFET）可以用形成足够厚的沟道区的外延层来制造，以使得JFET可用于高电压应用（例如具有大于约20V的击穿电压）。 另外或替代地，可以在栅极，源极和漏极区域中的一个或多个处引入阈值电压（VT）注入，以改善JFET的噪声性能。 另外，这样的JFET的制造可以促进与CMOS制造工艺和/或BiCMOS制造工艺同时形成整个JFET结构。

    System and method for charge restoration in a non-volatile memory device
    22.
    发明授权
    System and method for charge restoration in a non-volatile memory device 有权
    用于非易失性存储器件中的电荷恢复的系统和方法

    公开(公告)号：US06751146B1

    公开(公告)日：2004-06-15

    申请号：US10338333

    申请日：2003-01-07

    申请人： Zhigang Wang ,  Jianshi Wang ,  Imran Khan

    发明人： Zhigang Wang ,  Jianshi Wang ,  Imran Khan

    IPC分类号： G11C700

    CPC分类号： G11C16/3431 ,  G11C11/406 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/3418

    摘要： A non-volatile memory device comprising logic for charge restoration. The restore logic controls a read circuit for determining a value associated with the threshold voltage of a memory cell selected from a memory cell array, and compares the value to one or more boundary values to determine whether or not the memory cell value is out of bounds. In the event that the memory cell value is out of bounds, a target value for the memory cell is established. The restore logic controls a write circuit that applies a write pulse to the memory cell. The read and write process is repeated as necessary until the target value for the memory cell is achieved. The restore logic may include a processor for performing a statistical analysis on the memory cell array in order to determine target restoration values. Memory cells within the array may be reserved for use by the restore logic.

    摘要翻译： 一种包括用于电荷恢复的逻辑的非易失性存储器件。 恢复逻辑控制用于确定与从存储单元阵列选择的存储单元的阈值电压相关联的值的读取电路，并将该值与一个或多个边界值进行比较，以确定存储器单元值是否超出界限 。 在存储单元值超出范围的情况下，建立存储单元的目标值。 恢复逻辑控制将写入脉冲施加到存储器单元的写入电路。 必要时重复读取和写入过程，直到达到存储单元的目标值。 恢复逻辑可以包括用于对存储器单元阵列执行统计分析以便确定目标恢复值的处理器。 阵列内的存储单元可能被保留供恢复逻辑使用。

    EEPROM with reduced manufacturing complexity
    23.
    发明授权
    EEPROM with reduced manufacturing complexity 有权

    公开(公告)号：US06734491B1

    公开(公告)日：2004-05-11

    申请号：US10331705

    申请日：2002-12-30

    申请人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

    发明人： Jozef C. Mitros ,  Imran Khan ,  William Nehrer ,  Lou Hutter ,  Dirk Preikszat

    IPC分类号： H01L29788

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L29/42324

    摘要： A semiconductor device (200) comprising a semiconductor substrate (210) having source and drain regions (530, 540) located in the semiconductor substrate (210) and having similar doping profiles, wherein a channel region (550) extends from the source region (530) to the drain region (540). The semiconductor device (200) also comprises a dielectric layer (230) located over the source and drain regions (530, 540), the dielectric layer (230) having first and second thicknesses (T1, T2) wherein the second thickness (T2) is substantially less than the first thickness (T1) and is partially located over the channel region (550). The semiconductor device (200) also comprises a gate (510) located over the dielectric layer (230) wherein the second thickness (T2) is located between an end (515) of the gate (510) and one of the source and drain regions (530, 540).

    OPTIMIZED MACHINE LEARNING MARKETPLACE ASSISTANT
    25.
    发明申请
    OPTIMIZED MACHINE LEARNING MARKETPLACE ASSISTANT 有权

    公开(公告)号：US20220147706A1

    公开(公告)日：2022-05-12

    申请号：US17587732

    申请日：2022-01-28

    申请人： USMAN RANA ,  Imran Khan

    发明人： USMAN RANA ,  Imran Khan

    IPC分类号： G06F40/205 ,  G06F40/279 ,  G06F40/40 ,  G06Q30/06

    摘要： A method for implementing an automated assistant on one or more computing devices with a processor, a memory, and systems to receive an input at a computing device and parsing that input using a pragmatic natural language processor. A score is assigned to the input and a user intent is determined based on the assigned score. A user may search for a service or item and the system may generate a ranking of the item based on a number of attributes.

    Generic packet filtering
    26.
    发明授权
    Generic packet filtering 有权
    通用包过滤

    公开(公告)号：US08873367B2

    公开(公告)日：2014-10-28

    申请号：US13411146

    申请日：2012-03-02

    申请人： Michelle Perras ,  Juan Carlos Zuniga ,  Alexander Reznik ,  Reeteshkumar Varshney ,  Imran Khan

    发明人： Michelle Perras ,  Juan Carlos Zuniga ,  Alexander Reznik ,  Reeteshkumar Varshney ,  Imran Khan

    IPC分类号： H04W4/00 ,  H04L29/06 ,  H04W28/06

    CPC分类号： H04L69/22 ,  H04L69/14 ,  H04W28/06

    摘要： Embodiments contemplate one or more techniques for packet filtering. One or more embodiments may apply specific routing and/or forwarding rules on some or each packet when a device has one or more, or multiple, interfaces. Contemplated filtering techniques may be implemented in a module and/or without modifying an IP stack. The contemplated packet filtering techniques may apply to a terminal in uplink and/or downlink as well as to any network node. An incoming packet table may be created using 5-tuple, 6-tuple, and/or tags, among other mechanisms, to support incoming and/or outgoing packet filtering.

    摘要翻译： 实施例考虑了一种或多种用于分组过滤的技术。 一个或多个实施例可以在设备具有一个或多个或多个接口时在一些或每个分组上应用特定路由和/或转发规则。 考虑过滤技术可以在模块中实现和/或不修改IP堆栈。 预期的分组过滤技术可以应用于上行链路和/或下行链路中的终端以及任何网络节点。 可以使用5元组，6元组和/或标签以及其他机制来创建输入分组表，以支持传入和/或传出分组过滤。

    Low noise JFET
    29.
    发明授权
    Low noise JFET 有权
    低噪声JFET

    公开(公告)号：US08110857B2

    公开(公告)日：2012-02-07

    申请号：US12713866

    申请日：2010-02-26

    申请人： Pinghai Hao ,  Imran Khan ,  Joe Trogolo

    发明人： Pinghai Hao ,  Imran Khan ,  Joe Trogolo

    IPC分类号： H01L29/66

    CPC分类号： H01L29/8086 ,  H01L29/66901 ,  H01L29/808

    摘要： A low noise (1/f) junction field effect transistor (JFET) is disclosed, wherein multiple implants push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

    摘要翻译： 公开了一种低噪声（1 / f）结场效应晶体管（JFET），其中多个种植体推动晶体管的导电路径离开形成晶体管的层的表面。 以这种方式，导电路径中的电流不太可能受到可能存在于层的表面处的缺陷的干扰，从而减轻（1 / f）噪声。

    Method and apparatus for performing semiconductor memory operations
    30.
    发明授权
    Method and apparatus for performing semiconductor memory operations 有权
    用于执行半导体存储器操作的方法和装置

    公开(公告)号：US08040738B2

    公开(公告)日：2011-10-18

    申请号：US12346699

    申请日：2008-12-30

    申请人： Hagop Nazarian ,  Imran Khan ,  Chieu-Yin Chia

    发明人： Hagop Nazarian ,  Imran Khan ,  Chieu-Yin Chia

    IPC分类号： G11C11/34

    CPC分类号： G11C16/24 ,  G11C16/26 ,  G11C16/3454

    摘要： A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation.

    摘要翻译： 提供半导体存储器件和用于在半导体存储器件中执行存储器操作的方法。 半导体存储器件包括多个预定存储器阵列，位线解码器和控制器。 控制器向位线解码器提供存储器操作信号，并且在预充电多个预定存储器阵列的位线之后，根据存储器操作对多个预定存储器阵列中的一个或多个存储器单元中的选定存储单元执行存储器操作 信号。 位线解码器包括多个扇区选择晶体管，并且响应于存储器操作信号确定多个预定存储器阵列中的选定的行以及多个预定存储器阵列中的选定行中的选定行和未选择的行。 位线解码器还将多个预定存储器阵列的位线预先充电到第一电压电位，然后关闭多个预定存储器阵列中未选择的存储器阵列的扇区选择晶体管和多个预定存储器中的所选择的存储器的未选择的行 阵列，同时在所述控制器执行所述存储器操作之前，将所述多个预定存储器阵列中的选定行的选定行的扇区选择晶体管保持在所述第一电压电位。