公开(公告)号：US07102900B2

公开(公告)日：2006-09-05

申请号：US11045428

申请日：2005-01-27

Applicant: Donald R. Disney

Inventor： Donald R. Disney

IPC: H02M3/335

CPC classification number: H01L29/7803 ,  G05F1/14 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7802 ,  H01L29/7813 ,  H02M1/36 ,  H02M3/335 ,  H02M3/33507 ,  H02M3/33553 ,  H02M3/33561 ,  H02M2001/0009

Abstract: A technique for controlling a power supply with power supply control element with a tap element. In one embodiment, a power supply regulator includes a power transistor having first, second, third and fourth terminals. A control circuit is included, which is coupled to the third and fourth terminals of the power transistor. The power transistor is configured to switch a current between the first and second terminals in response a control signal received from the control circuit at the third terminal. A voltage between the fourth and second terminals of the power transistor is substantially proportional to a current flowing between the first and second terminals when a voltage between the first and second terminals is less than a pinch off voltage. The voltage between the fourth and second terminals of the power transistor is substantially constant and less than the voltage between the first and second terminals when the voltage between the first and second terminals is greater than the pinch off voltage.

Abstract translation: 一种用电源控制元件与抽头元件控制电源的技术。 在一个实施例中，电源调节器包括具有第一，第二，第三和第四端子的功率晶体管。 包括控制电路，其耦合到功率晶体管的第三和第四端子。 功率晶体管被配置为响应于从第三端子处的控制电路接收的控制信号在第一和第二端子之间切换电流。 当第一和第二端子之间的电压小于夹断电压时，功率晶体管的第四和第二端子之间的电压基本上与在第一和第二端子之间流动的电流成比例。 当第一和第二端子之间的电压大于夹断电压时，功率晶体管的第四和第二端子之间的电压基本上是恒定的，并且小于第一和第二端子之间的电压。

公开(公告)号：US06828631B2

公开(公告)日：2004-12-07

申请号：US10839043

申请日：2004-05-05

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L2976

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

公开(公告)号：US06800903B2

公开(公告)日：2004-10-05

申请号：US09961229

申请日：2001-09-20

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L2976

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

公开(公告)号：US06787437B2

公开(公告)日：2004-09-07

申请号：US10163536

申请日：2002-06-06

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L21425

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract translation: 高电压绝缘栅场效应晶体管包括具有源极和漏极的绝缘栅场效应器件结构，漏极形成有一个延伸的阱区，其具有夹在其中的一个或多个相反导电类型的掩埋层。 一个或多个掩埋层在阱区域的延伸部分中产生相关联的多个并联JFET传导通道。 并联JFET导通通道为HVFET提供低导通状态电阻。

公开(公告)号：US06768172B2

公开(公告)日：2004-07-27

申请号：US10368065

申请日：2003-02-18

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L2976

CPC classification number: H01L29/7816 ,  H01L21/26 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

公开(公告)号：US06639277B2

公开(公告)日：2003-10-28

申请号：US09961235

申请日：2001-09-20

Applicant: Valdimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Valdimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L2976

CPC classification number: H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

公开(公告)号：US06633065B2

公开(公告)日：2003-10-14

申请号：US09961221

申请日：2001-09-20

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L31113

CPC classification number: H01L29/7816 ,  H01L21/26 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66674 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7832 ,  H01L29/7835

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract translation: 高电压绝缘栅场效应晶体管包括具有源极和漏极的绝缘栅场效应器件结构，漏极形成有一个延伸的阱区，其具有夹在其中的一个或多个相反导电类型的掩埋层。 一个或多个掩埋层在阱区域的延伸部分中产生相关联的多个并联JFET传导通道。 并联JFET导通通道使HVFET具有低导通状态电阻。

公开(公告)号：US06168983A

公开(公告)日：2001-01-02

申请号：US09245029

申请日：1999-02-05

Applicant: Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

Inventor： Vladimir Rumennik ,  Donald R. Disney ,  Janardhanan S. Ajit

IPC: H01L21337

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/0873 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. A minimal number of processing steps are required to form the parallel JFET conduction channels which provide the HVFET with a low on-state resistance.

Abstract translation: 一种用于制造具有源极和漏极的绝缘栅场效应器件结构的高电压绝缘栅场效应晶体管的方法包括以下步骤：用具有一个或多个相反导电类型的掩埋层的扩展阱区形成漏极 夹在里面 一个或多个掩埋层在阱区域的延伸部分中产生相关联的多个并联JFET传导通道。 需要最少数量的处理步骤来形成并联JFET导通通道，其为HVFET提供低导通状态电阻。

公开(公告)号：US5545915A

公开(公告)日：1996-08-13

申请号：US376566

申请日：1995-01-23

Applicant: Donald R. Disney ,  Wayne A. Sozansky ,  James M. Himelick

Inventor： Donald R. Disney ,  Wayne A. Sozansky ,  James M. Himelick

IPC: H01L23/58 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7802 ,  H01L23/585 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L2924/0002 ,  Y10S148/044

Abstract: A semiconductor device characterized by a field limiting ring formed by a number of field limiting cells that define wells which are laterally diffused to form a continuous equipotential ring between interior and exterior regions of a semiconductor device. A number of active cells are formed in the interior region, and are therefore delineated from the exterior region of the device. Each of these active cells is a transistor, and preferably a field-effect transistor, whose structure is essentially identical to the field limiting cells, except that their wells are not merged but instead are isolated from each other. The field limiting ring increases the breakdown voltage and the ruggedness of device, and therefore enables the device to sustain high voltages when the device is in the off-state. The process does not require masking, implanting and diffusion steps for the sole purpose of forming the field limiting ring, but is instead fully integrated with the semiconductor process for forming the active cells. The field limiting cells also contribute to forward current conduction when the device is in the on-state, thereby lowering the on-resistance of the device.

Abstract translation: 一种半导体器件，其特征在于由许多场限制电池形成的场限制环，所述场限制电池限定了横向扩散以在半导体器件的内部和外部区域之间形成连续等电位环的阱。 在内部区域中形成多个活性细胞，因此从装置的外部区域划出。 这些有源电池中的每一个都是晶体管，优选场效应晶体管，其结构基本上与场限制电池相同，不同之处在于它们的阱不被合并，而是相互隔离。 场限制环增加了击穿电压和器件的坚固性，因此当器件处于关断状态时，器件能够维持高电压。 该方法不需要用于形成场限制环的唯一目的的掩蔽，植入和扩散步骤，而是与用于形成活性细胞的半导体工艺完全整合。 当器件处于导通状态时，场限制单元还有助于正向电流传导，从而降低器件的导通电阻。

公开(公告)号：US08981432B2

公开(公告)日：2015-03-17

申请号：US13572408

申请日：2012-08-10

Applicant: Hui Nie ,  Donald R. Disney ,  Isik C. Kizilyalli

Inventor： Hui Nie ,  Donald R. Disney ,  Isik C. Kizilyalli

IPC: H01L29/80

CPC classification number: H01L21/0254 ,  H01L21/02645 ,  H01L21/6835 ,  H01L24/83 ,  H01L29/2003 ,  H01L29/66204 ,  H01L29/66212 ,  H01L29/66356 ,  H01L29/66446 ,  H01L29/739 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872 ,  H01L2221/68327 ,  H01L2224/04026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.

Abstract translation: 一种制造电子器件的方法包括提供包括III族氮化物种子层的工程化衬底结构，形成与III族氮化物种子层耦合的GaN基功能层，以及形成电耦合到至少一部分 GaN基功能层。 该方法还包括将与GaN基功能层相对的载体衬底接合并去除工程衬底结构的至少一部分。 该方法还包括形成电耦合到GaN基功能层的至少另一部分并去除载体衬底的第二电极结构。