公开(公告)号：US11462626B2

公开(公告)日：2022-10-04

申请号：US16900292

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wei Hsu ,  Pei Ying Lai ,  Cheng-Hao Hou ,  Xiong-Fei Yu ,  Chi On Chui

IPC: H01L27/088 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

公开(公告)号：US20220310445A1

公开(公告)日：2022-09-29

申请号：US17325477

申请日：2021-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L21/768 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/522

Abstract: In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

公开(公告)号：US20220254901A1

公开(公告)日：2022-08-11

申请号：US17728296

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

公开(公告)号：US20220238687A1

公开(公告)日：2022-07-28

申请号：US17220076

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: In an embodiment, a device includes: a p-type transistor including: a first channel region; a first gate dielectric layer on the first channel region; a tungsten-containing work function tuning layer on the first gate dielectric layer; and a first fill layer on the tungsten-containing work function tuning layer; and an n-type transistor including: a second channel region; a second gate dielectric layer on the second channel region; a tungsten-free work function tuning layer on the second gate dielectric layer; and a second fill layer on the tungsten-free work function tuning layer.

公开(公告)号：US20220223594A1

公开(公告)日：2022-07-14

申请号：US17182733

申请日：2021-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

公开(公告)号：US11342334B2

公开(公告)日：2022-05-24

申请号：US16901885

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/423

Abstract: An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

公开(公告)号：US20220140151A1

公开(公告)日：2022-05-05

申请号：US17574844

申请日：2022-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Chien Ning Yao ,  Chi On Chui

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.

公开(公告)号：US20220140101A1

公开(公告)日：2022-05-05

申请号：US17577169

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/786

Abstract: A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

公开(公告)号：US11302793B2

公开(公告)日：2022-04-12

申请号：US16943110

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/49

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.

公开(公告)号：US20220102152A1

公开(公告)日：2022-03-31

申请号：US17038499

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8238

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.