公开(公告)号：US20140003492A1

公开(公告)日：2014-01-02

申请号：US13932929

申请日：2013-07-01

Applicant: Qualcomm Incorporated

Inventor： Ying Chen ,  Ye-Kui Wang

IPC: H04N7/26

CPC classification number: H04N19/13 ,  H04N19/117 ,  H04N19/124 ,  H04N19/184 ,  H04N19/30 ,  H04N19/51 ,  H04N19/597 ,  H04N19/61 ,  H04N19/70

Abstract: A device for processing video data can be configured to receive in a video parameter set, one or more syntax elements that include information related to session negotiation; receive in the video data a first sequence parameter set comprising a first syntax element identifying the video parameter set; receive in the video data a second sequence parameter set comprising a second syntax element identifying the video parameter set; process, based on the one or more syntax elements, a first set of video blocks associated with the first parameter set and a second set of video blocks associated with the second parameter set.

Abstract translation: 用于处理视频数据的设备可以被配置为在视频参数集中接收包括与会话协商有关的信息的一个或多个语法元素; 在视频数据中接收包括识别视频参数集的第一语法元素的第一序列参数集; 在所述视频数据中接收包括识别所述视频参数集的第二语法元素的第二序列参数集; 基于所述一个或多个语法元素处理与所述第一参数集相关联的第一组视频块和与所述第二参数集相关联的第二组视频块。

公开(公告)号：US20130135433A1

公开(公告)日：2013-05-30

申请号：US13689508

申请日：2012-11-29

Applicant: Qualcomm Incorporated

Inventor： Ying Chen ,  Ye-Kui Wang

IPC: H04N13/00

CPC classification number: H04N19/50 ,  H04N13/10 ,  H04N13/161 ,  H04N19/176 ,  H04N19/423 ,  H04N19/597 ,  H04N19/70

Abstract: In general, techniques are described for separately coding depth and texture components of video data. A video coding device configured to code video data may perform the techniques. The video coding device may comprise a decoded picture buffer and a processor configured to store a depth component in the decoded picture buffer, analyze a view dependency to determine whether the depth component is used for inter-view prediction and remove the depth component from the decoded picture buffer in response to determining that the depth component is not used for inter-view prediction. for processing video data including a view component comprised of a depth component and a texture component

Abstract translation: 通常，描述用于分别编码视频数据的深度和纹理分量的技术。 被配置为对视频数据进行编码的视频编码装置可以执行这些技术。 视频编码装置可以包括解码图像缓冲器和被配置为在解码图像缓冲器中存储深度分量的处理器，分析视图依赖性以确定深度分量是否用于视角间预测，并从解码的图像缓冲器中去除深度分量 响应于确定深度分量不用于视域间预测的图像缓冲器。 用于处理包括由深度分量和纹理分量组成的视图分量的视频数据

公开(公告)号：US20130107953A1

公开(公告)日：2013-05-02

申请号：US13664279

申请日：2012-10-30

Applicant: Qualcomm Incorporated

Inventor： Ying Chen ,  Ye-Kui Wang ,  Jianle Chen

IPC: H04N7/32

CPC classification number: H04N19/172 ,  H04N19/107 ,  H04N19/132 ,  H04N19/177 ,  H04N19/423 ,  H04N19/44 ,  H04N19/463 ,  H04N19/573 ,  H04N19/58 ,  H04N19/70

Abstract: As one example, techniques for decoding video data include receiving a bitstream that includes one or more pictures of a coded video sequence (CVS), decoding a first picture according to a decoding order, wherein the first picture is a random access point (RAP) picture that is not an instantaneous decoding refresh (IDR) picture, and decoding at least one other picture following the first picture according to the decoding order based on the decoded first picture. As another example, techniques for encoding video data include generating a bitstream that includes one or more pictures of a CVS, wherein a first picture according to the decoding order is a RAP picture that is not an IDR picture, and avoiding including at least one other picture, other than the first picture, that corresponds to a leading picture associated with the first picture, in the bitstream.

Abstract translation: 作为一个示例，用于解码视频数据的技术包括接收包括编码视频序列（CVS）的一个或多个图像的比特流，根据解码顺序解码第一图像，其中第一图像是随机接入点（RAP） 图像，其不是瞬时解码刷新（IDR）图像，并且基于解码的第一图像根据解码顺序对第一图像之后的至少一个其他图像进行解码。 作为另一示例，用于编码视频数据的技术包括生成包括CVS的一个或多个图片的比特流，其中根据解码顺序的第一图片是不是IDR图片的RAP图片，并且避免包括至少一个其他 在比特流中对应于与第一图像相关联的前导图像的第一图像之外的图像。

公开(公告)号：US20130107942A1

公开(公告)日：2013-05-02

申请号：US13664057

申请日：2012-10-30

Applicant: Qualcomm Incorporated

Inventor： Ying Chen ,  Ye-Kui Wang ,  Rajan Laxman Joshi ,  Marta Karczewicz

IPC: H04N7/26

CPC classification number: H04N19/66 ,  H04N19/463 ,  H04N19/70

Abstract: A video encoder generates a first network abstraction layer (NAL) unit. The first NAL unit contains a first fragment of a parameter set associated with video data. The video encoder also generates a second NAL unit. The second NAL unit contains a second fragment of the parameter set. A video decoder may receive a bitstream that includes the first and second NAL units. The video decoder decodes, based at least in part on the parameter set, one or more coded pictures of the video data.

Abstract translation: 视频编码器生成第一网络抽象层（NAL）单元。 第一个NAL单元包含与视频数据相关联的参数集的第一个片段。 视频编码器还产生第二NAL单元。 第二个NAL单元包含参数集的第二个片段。 视频解码器可以接收包括第一和第二NAL单元的比特流。 视频解码器至少部分地基于参数集来解码视频数据的一个或多个编码图像。

公开(公告)号：US20130101035A1

公开(公告)日：2013-04-25

申请号：US13658453

申请日：2012-10-23

Applicant: Qualcomm Incorporated

Inventor： Ye-Kui Wang ,  Ying Chen ,  Muhammed Zeyd Coban ,  Marta Karczewicz

IPC: H04N7/32 ,  H04N7/26

CPC classification number: H04N19/436 ,  H04N19/17 ,  H04N19/174 ,  H04N19/46 ,  H04N19/61 ,  H04N19/70 ,  H04N19/895

Abstract: Techniques described herein for coding video data include techniques for coding pictures partitioned into tiles, in which each of the plurality of tiles in a picture is assigned to one of a plurality of tile groups. One example method for coding video data comprising a picture that is partitioned into a plurality tiles comprises coding video data in a bitstream, and coding, in the bitstream, information that indicates one of a plurality of tile groups to which each of the plurality of tiles is assigned. The techniques for grouping tiles described herein may facilitate improved parallel processing for both encoding and decoding of video bitstreams, improved error resilience, and more flexible region of interest (ROI) coding.

Abstract translation: 本文描述的用于编码视频数据的技术包括用于对分割成瓦片的图像进行编码的技术，其中将图片中的多个瓦片中的每一个分配给多个瓦片组中的一个。 用于编码视频数据的一个示例性方法包括分割成多个片的图像包括：对比特流中的视频数据进行编码，以及在比特流中编码指示多个瓦片组中的每一个的多个瓦片组之一的信息 被分配。 用于分组的瓦片的技术可以促进对视频比特流的编码和解码的改进的并行处理，改善的错误弹性以及更灵活的感兴趣区域（ROI）编码。

公开(公告)号：US11490119B2

公开(公告)日：2022-11-01

申请号：US17079459

申请日：2020-10-24

Applicant: QUALCOMM Incorporated

Inventor： Ye-Kui Wang ,  Ying Chen

IPC: H04N19/58 ,  H04N19/70 ,  H04N7/12 ,  H04N19/105 ,  H04N19/176 ,  H04N19/463 ,  H04N19/174 ,  H04N19/50

Abstract: Techniques are described related to output and removal of decoded pictures from a decoded picture buffer (DPB). The example techniques may remove a decoded picture from the DPB prior to coding a current picture. For instance, the example techniques may remove the decoded picture if that decoded picture is not identified in the reference picture set of the current picture.

公开(公告)号：US11477253B2

公开(公告)日：2022-10-18

申请号：US15208355

申请日：2016-07-12

Applicant: QUALCOMM Incorporated

Inventor： Michael G. Luby ,  Mark Watson ,  Lorenzo Vicisano ,  Payam Pakzad ,  Bin Wang ,  Ying Chen ,  Thomas Stockhammer

IPC: H04L29/06 ,  H04N21/231 ,  H04N21/234 ,  H04N21/2343 ,  H04N21/235 ,  H04N21/258 ,  H04N21/2662 ,  H04N21/435 ,  H04N21/44 ,  H04N21/4402 ,  H04N21/442 ,  H04N21/84 ,  H04N21/845 ,  H04L29/08 ,  H04N21/24 ,  H04L65/60 ,  H04L65/612 ,  H04L67/02 ,  H04L65/80

Abstract: A block-request streaming system provides for improvements in the user experience and bandwidth efficiency of such systems, typically using an ingestion system that generates data in a form to be served by a conventional file server (HTTP, FTP, or the like), wherein the ingestion system intakes content and prepares it as files or data elements to be served by the file server. The system might include controlling the sequence, timing and construction of block requests, time based indexing, variable block sizing, optimal block partitioning, control of random access point placement, including across multiple presentation versions, dynamically updating presentation data, and/or efficiently presenting live content and time shifting.

公开(公告)号：US20220295076A1

公开(公告)日：2022-09-15

申请号：US17657563

申请日：2022-03-31

Applicant: QUALCOMM Incorporated

Inventor： Ying Chen ,  Marta Karczewicz ,  Ye-Kui Wang

IPC: H04N19/157 ,  H04N19/46 ,  H04N19/172 ,  H04N19/122

Abstract: A video encoder is configured to determine a picture size for one or more pictures included in a video sequence. The picture size associated with the video sequence may be a multiple of an aligned coding unit size for the video sequence. In one example, the aligned coding unit size for the video sequence may comprise a minimum coding unit size where the minimum coding unit size is selected from a plurality of smallest coding unit sizes corresponding to different pictures in the video sequence. A video decoder is configured to obtain syntax elements to determine the picture size and the aligned coding unit size for the video sequence. The video decoder decodes the pictures included in the video sequence with the picture size, and stores the decoded pictures in a decoded picture buffer.

公开(公告)号：US11068741B2

公开(公告)日：2021-07-20

申请号：US16224644

申请日：2018-12-18

Applicant: QUALCOMM Incorporated

Inventor： Lei Wang ,  Ning Bi ,  Ying Chen

IPC: G06K9/00 ,  G06K9/62 ,  G06K9/52 ,  G06T7/50 ,  G06K9/42 ,  G06K9/46

Abstract: Techniques and systems are provided for determining features for one or more objects in one or more video frames. For example, an image of an object, such as a face, can be received, and features of the object in the image can be identified. A size of the object can be determined based on the image, for example based on inter-eye distance of a face. Based on the size, either a high-resolution set of features or a low-resolution set of features is selected to compare to the features of the object. The object can be identified by matching the features of the object to matching features from the selected set of features.

公开(公告)号：US11039129B2

公开(公告)日：2021-06-15

申请号：US15895815

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Li Zhang ,  Hongbin Liu ,  Ying Chen

IPC: H04N19/107 ,  H04N19/597 ,  H04N19/70 ,  H04N19/463 ,  H04N19/159 ,  H04N19/182 ,  H04N19/91 ,  H04N7/12

Abstract: This disclosure describes techniques for signaling and processing information indicating simplified depth coding (SDC) for depth intra-prediction and depth inter-prediction modes in a 3D video coding process, such as a process defined by the 3D-HEVC extension to HEVC. In some examples, the disclosure describes techniques for unifying the signaling of SDC for depth intra-prediction and depth inter-prediction modes in 3D video coding. The signaling of SDC can be unified so that a video encoder or video decoder uses the same syntax element for signaling SDC for both the depth intra-prediction mode and the depth inter-prediction mode. Also, in some examples, a video coder may signal and/or process a residual value generated in the SDC mode using the same syntax structure, or same type of syntax structure, for both the depth intra-prediction mode and depth inter-prediction mode.