公开(公告)号：US20130335522A1

公开(公告)日：2013-12-19

申请号：US13772917

申请日：2013-02-21

Applicant: QUALCOMM INCORPORATED

Inventor： Li Zhang ,  Ying Chen ,  Marta Karczewicz

IPC: H04N7/26

CPC classification number: H04N19/52 ,  H04N19/46 ,  H04N19/597

Abstract: In some example techniques for generating and updating depth map estimates used for inter-view motion prediction and/or inter-view residual prediction for coding multiview video data, each of a plurality of dependent views is associated with a dependent depth view estimate, which may be generated or updated based on coding of the texture data of the dependent view relative to a base view. In such examples, each of the dependent depth map estimates may be warped to the base view to produce a respective one of a plurality of base depth map estimates. Each dependent depth map estimate and the respective base depth map estimate for a depth map estimate pair associated with the respective one of the plurality of dependent views.

Abstract translation: 在用于生成和更新用于视频间运动预测和/或用于编码多视点视频数据的视频间残差预测的深度图估计的一些示例性技术中，多个从属视图中的每一个与依赖深度视图估计相关联， 基于相对于基本视图的从属视图的纹理数据的编码来生成或更新。 在这样的示例中，依赖深度图估计中的每一个可以被扭曲到基本视图以产生多个基本深度图估计中的相应的一个。 每个相关深度图估计和与多个从属视图中的相应一个相关联的深度图估计对的相应基准深度图估计。

公开(公告)号：US12081780B2

公开(公告)日：2024-09-03

申请号：US16982013

申请日：2018-03-19

Applicant: Qualcomm Incorporated

Inventor： Yu Han ,  Kai Zhang ,  Li Zhang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/44 ,  H04N19/105 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

Abstract: Methods and devices for decoding including a processor configured to determine which picture is a collocated picture, and determine a location of an associated block of the video data in the collocated picture that corresponds to the current block of video data in the current coding picture, based on using previously decoded blocks in the current coding picture to find an initial motion vector between the associated block in the collocated picture and the current block in the current coding picture, where the associated block of the video data includes at least one first derived motion vector. The processor configured to determine at least one second derived motion vector associated with the current block in the current coding picture, when the initial motion vector points to the collocated picture, based on the at least on first derived motion vector associated with the associated block in the collocated picture.

公开(公告)号：US12052428B2

公开(公告)日：2024-07-30

申请号：US17804777

申请日：2022-05-31

Applicant: QUALCOMM Incorporated

Inventor： Kai Zhang ,  Jianle Chen ,  Li Zhang ,  Xiang Li ,  Marta Karczewicz

IPC: H04N19/159 ,  H04N19/107 ,  H04N19/11 ,  H04N19/124 ,  H04N19/139 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/44 ,  H04N19/463 ,  H04N19/503 ,  H04N19/513 ,  H04N19/593

CPC classification number: H04N19/159 ,  H04N19/107 ,  H04N19/11 ,  H04N19/124 ,  H04N19/139 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/463 ,  H04N19/503 ,  H04N19/513 ,  H04N19/593 ,  H04N19/186

Abstract: Techniques are described for using an inter-intra-prediction block. A video coder may generate a first prediction block according to an intra-prediction mode and generate a second prediction block according to an inter-prediction mode. The video coder may weighted combine, such as based on the intra-prediction mode, the two prediction blocks to generate an inter-intra-prediction block (e.g., final prediction block). In some examples, an inter-intra candidate is identified in a list of candidate motion vector predictors, and an inter-intra-prediction block is used based on identification of the inter-intra candidate in the list of candidate motion vector predictors.

公开(公告)号：US20230276069A1

公开(公告)日：2023-08-31

申请号：US18312904

申请日：2023-05-05

Applicant: QUALCOMM Incorporated

Inventor： Yi-Wen Chen ,  Wei-Jung Chien ,  Yu-Chen Sun ,  Li Zhang ,  Sungwon Lee ,  Xiang Li ,  Hsiao-Chiang Chuang ,  Jianle Chen ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/70 ,  H04N19/44 ,  H04N19/176 ,  H04N19/54

CPC classification number: H04N19/52 ,  H04N19/70 ,  H04N19/44 ,  H04N19/176 ,  H04N19/54 ,  H04N19/593

Abstract: A video coder may determine a motion vector of a non-adjacent block of a current picture of the video data. The non-adjacent block is non-adjacent to a current block of the current picture. Furthermore, the video coder determines, based on the motion vector of the non-adjacent block, a motion vector predictor (MVP) for the current block. The video coder may determine a motion vector of the current block. The video coder may also determine a predictive block based on the motion vector of the current block.

公开(公告)号：US11425387B2

公开(公告)日：2022-08-23

申请号：US16926337

申请日：2020-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kai Zhang ,  Li Zhang ,  Wei-Jung Chien ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/132 ,  H04N19/136 ,  H04N19/176 ,  H04N19/186 ,  H04N19/573 ,  H04N19/593

Abstract: A method of processing video data includes determining, by processing circuitry, a plurality of neighboring samples for predicting a current block. The plurality of neighboring samples are arranged outside of a region of a current picture, the region comprising the current block, a row of samples adjacent to a top row of the current block, and a column of samples adjacent to a left column of the current block. The method further comprises deriving, by the processing circuitry, local illumination compensation information for the current block using the plurality of neighboring samples and generating, by the processing circuitry, a prediction block using the local illumination compensation information.

公开(公告)号：US11310536B2

公开(公告)日：2022-04-19

申请号：US16452315

申请日：2019-06-25

Applicant: QUALCOMM Incorporated

Inventor： Li Zhang ,  Wei-Jung Chien ,  Jianle Chen ,  Xin Zhao ,  Marta Karczewicz

IPC: H04N19/176 ,  H04N19/593 ,  H04N19/11 ,  H04N19/159 ,  H04N19/186 ,  H04N19/70 ,  H04N19/105 ,  H04N19/96 ,  H04N19/463 ,  H04N19/46 ,  H04N19/124 ,  H04N19/91

Abstract: An example device includes a memory and processing circuitry in communication with the memory. The processing circuitry of a device is configured to form a most probable mode (MPM) candidate list for a chroma block of the video data stored to the memory, such that the MPM candidate list includes one or more derived modes (DMs) associated with a luma block of the video data associated with the chroma block, and a plurality of luma prediction modes that can be used for coding luminance components of the video data. The processing circuitry is further configured to select a mode from the MPM candidate list, and to code the chroma block according to the mode selected from the MPM candidate list.

公开(公告)号：US20220070486A1

公开(公告)日：2022-03-03

申请号：US17454456

申请日：2021-11-10

Applicant: QUALCOMM Incorporated

Inventor： Yi-Wen Chen ,  Wei-Jung Chien ,  Yu-Chen Sun ,  Li Zhang ,  Sungwon Lee ,  Xiang Li ,  Hsiao-Chiang Chuang ,  Jianle Chen ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/70 ,  H04N19/44 ,  H04N19/176 ,  H04N19/54

Abstract: A video coder may determine a motion vector of a non-adjacent block of a current picture of the video data. The non-adjacent block is non-adjacent to a current block of the current picture. Furthermore, the video coder determines, based on the motion vector of the non-adjacent block, a motion vector predictor (MVP) for the current block. The video coder may determine a motion vector of the current block. The video coder may also determine a predictive block based on the motion vector of the current block.

公开(公告)号：US11265551B2

公开(公告)日：2022-03-01

申请号：US16249371

申请日：2019-01-16

Applicant: QUALCOMM Incorporated

Inventor： Yi-Wen Chen ,  Wei-Jung Chien ,  Yu-Chen Sun ,  Li Zhang ,  Hsiao-Chiang Chuang ,  Marta Karczewicz

IPC: H04N19/139 ,  H04N19/105 ,  H04N19/577 ,  H04N19/513 ,  H04N19/176 ,  H04N19/44 ,  H04N19/57

Abstract: Improved systems and methods related to decoder-side motion vector derivation (DMVD), for example, in applying one or more constraints to motion information, such as a MV derived by DMVD, and/or a MV difference between an initial MV and an MV derived by DMVD. These techniques may be applied to any of the existing video codecs, such as HEVC (High Efficiency Video Coding), and/or may be an efficient coding tool in any future video coding standards. In one example, the block size used for DMVD can be restricted. In another example, FRUC bilateral matching can be simplified by not searching outside reference blocks indicated by the original motion vector.

公开(公告)号：US11233998B2

公开(公告)日：2022-01-25

申请号：US15166144

申请日：2016-05-26

Applicant: QUALCOMM Incorporated

Inventor： Li Zhang ,  Marta Karczewicz ,  Jianle Chen

IPC: H04N19/13 ,  H04N19/174 ,  H04N19/124 ,  H04N19/136 ,  H04N19/122 ,  H04N19/176 ,  H04N19/91 ,  H04N19/17 ,  H04N19/436 ,  H04N19/625 ,  H04N19/126 ,  H04N19/159 ,  H04N19/577 ,  H04N19/172 ,  H04N19/157 ,  H04N19/184

Abstract: A video coding device includes a memory configured to store video data and processor(s) configured to process at least a portion of the stored video data. The processor(s) are configured to identify a coefficient group (CG) that includes a current transform coefficient of the video data, the CG representing a subset of transform coefficients within a transform unit. The processor(s) are further configured to determine a size of the CG based on a combination of a transform size and one or both of (i) a coding mode associated with the transform unit, or (ii) a transform matrix associated with the transform unit.

公开(公告)号：US11064195B2

公开(公告)日：2021-07-13

申请号：US15432857

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Marta Karczewicz ,  Wei-Jung Chien ,  Li Zhang

IPC: H04N7/12 ,  H04N19/117 ,  H04N19/14 ,  H04N19/70 ,  H04N19/82 ,  H04N19/463 ,  H04N19/136 ,  H04N19/176 ,  H04N19/80

Abstract: In one example, a device includes a memory configured to store video data, and one or more processing units implemented in circuitry configured to construct a plurality of filters for classes of blocks of a current picture of the video data, wherein to construct the plurality of filters, the one or more processing units are configured to generate a plurality of sets of filter coefficients, and for a subset of the plurality of filters, determine respective indexes that identify one of the sets of filter coefficients for the corresponding filter of the subset; decode a current block of the current picture, determine a class for the current block, select a filter of the plurality of filters that corresponds to the class for the current block, and filter at least one pixel of the current block using the selected filter.