公开(公告)号：US11532734B2

公开(公告)日：2022-12-20

申请号：US16370449

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/34 ,  H01L29/08 ,  H01L21/02 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having germanium nanowire channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium nanowire channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, each of the nanowires including germanium, and the fin including a defect modification layer on a first semiconductor layer, a second semiconductor layer on the defect modification layer, and a third semiconductor layer on the second semiconductor layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11515140B2

公开(公告)日：2022-11-29

申请号：US16409706

申请日：2019-05-10

Applicant: SiCrystal GmbH

Inventor： Bernhard Ecker ,  Ralf Müller ,  Matthias Stockmeier ,  Michael Vogel ,  Arnd-Dietrich Weber

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/34 ,  H01L29/04 ,  C30B29/36 ,  C30B23/02

Abstract: The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

公开(公告)号：US11437490B2

公开(公告)日：2022-09-06

申请号：US16843262

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Haiting Wang

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/51 ,  H01L21/02 ,  H01L29/34

Abstract: One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.

公开(公告)号：US20220157945A1

公开(公告)日：2022-05-19

申请号：US17667201

申请日：2022-02-08

Applicant: ROHM CO., LTD.

Inventor： Kentaro TAMURA

IPC: H01L29/16 ,  H01L29/872 ,  H01L29/47 ,  H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L21/02 ,  C30B25/20 ,  C23C16/32 ,  C30B25/18 ,  C30B29/36 ,  H01L29/34 ,  H01L29/78

Abstract: The SiC epitaxial wafer includes a substrate, and an SiC epitaxial growth layer disposed on the substrate, wherein an Si compound gas is used for a supply source of Si, and a Carbon (C) compound gas is used as a supply source of C, for the SiC epitaxial growth layer, wherein any one or both of the Si compound gas and the C compound gas is provided with a compound gas containing Fluorine (F), as the supply source. The Si compound is generally expressed with SinHxClyFz (n>=1, x>=0, y>=0, z>=1, x+y+z=2n+2), and the C compound is generally expressed with CmHqClrFs (m>=1, q>=0, r>=0, s>=1, q+r+s=2m+2) . There are provided a high quality SiC epitaxial wafer having few surface defects and having excellent film thickness uniformity and carrier density uniformity, a manufacturing apparatus of such an SiC epitaxial wafer, a fabrication method of such an SiC epitaxial wafer, and a semiconductor device.

公开(公告)号：US11177377B2

公开(公告)日：2021-11-16

申请号：US16726263

申请日：2019-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/34

Abstract: A mesa structure includes a substrate. A mesa protrudes out of the substrate. The mesa includes a slope and a top surface. The slope surrounds the top surface. A lattice damage area is disposed at inner side of the slope. The mesa can optionally further includes an insulating layer covering the lattice damage area. The insulating layer includes an oxide layer or a nitride layer.

公开(公告)号：US11171015B2

公开(公告)日：2021-11-09

申请号：US16567290

申请日：2019-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Chen-Hao Chiang ,  Alexander Kalnitsky ,  Yeur-Luen Tu ,  Eugene Chen

IPC: H01L21/322 ,  H01L23/66 ,  H01L21/762 ,  H01L29/34 ,  H01L29/06

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

公开(公告)号：US20210210602A1

公开(公告)日：2021-07-08

申请号：US17055542

申请日：2019-04-08

Applicant: SCIOCS COMPANY LIMITED ,  SUMITOMO CHEMICAL COMPANY, LIMITED

Inventor： Takeshi MEGURO ,  Junichiro TAKEDA ,  Hiroyuki TOMIOKA

IPC: H01L29/10 ,  H01L29/34 ,  H01L29/20 ,  H01L29/778

Abstract: Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 μm or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.

公开(公告)号：US20210184115A1

公开(公告)日：2021-06-17

申请号：US17167295

申请日：2021-02-04

Applicant: Quantum Silicon Inc.

Inventor： Robert A. Wolkow ,  Roshan Achal ,  Taleana Huff ,  Hatem Labidi ,  Lucian Livadaru ,  Paul Piva ,  Mohammad Rashidi

IPC: H01L45/00 ,  H01L27/24 ,  H01L29/66 ,  H01L29/34 ,  H01L29/12 ,  H01L29/76 ,  H01L49/00

Abstract: A multiple-atom germanium quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated germanium surface, each dangling bonds having one of three ionization states of +1, 0 or −1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the germanium band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed.

公开(公告)号：US10943790B2

公开(公告)日：2021-03-09

申请号：US16391006

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Tsz-Mei Kwok

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/06 ,  H01L29/36 ,  H01L21/02 ,  H01L29/08 ,  H01L29/34

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.

公开(公告)号：US10937959B2

公开(公告)日：2021-03-02

申请号：US16318626

申请日：2017-07-19

Applicant: Quantum Silicon Inc.

Inventor： Robert A. Wolkow ,  Roshan Achal ,  Taleana Huff ,  Hatem Labidi ,  Lucian Livadaru ,  Paul Piva ,  Mohammad Rashidi

IPC: H01L45/00 ,  H01L27/24 ,  H01L29/66 ,  H01L29/34 ,  H01L29/12 ,  H01L29/76 ,  H01L49/00 ,  B82Y10/00 ,  B82Y30/00

Abstract: A multiple-atom silicon quantum dot is provided that includes multiple dangling bonds on an otherwise H-terminated silicon surface, each dangling bonds having one of three ionization states of +1, 0 or −1 and corresponding respectively to 0, 1, or 2 electrons in a dangling bond state. The dangling bonds together in close proximity and having the dangling bond states energetically in the silicon band gap with selective control of the ionization state of one of the dangling bonds. A new class of electronics elements is provided through the inclusion of at least one input and at least one output to the multiple dangling bonds. Selective modification or creation of a dangling bond is also detailed.