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    RECEIVER SYNCHRONIZATION FOR LIGHT COMMUNICATIONS
    11.
    发明公开
    RECEIVER SYNCHRONIZATION FOR LIGHT COMMUNICATIONS 审中-公开

    公开(公告)号：US20230308254A1

    公开(公告)日：2023-09-28

    申请号：US18125412

    申请日：2023-03-23

    申请人： The Regents of the University of Michigan

    发明人： Jethro REIMANN ,  Michael PUTTY ,  Sridhar LAKSHMANAN

    IPC分类号： H04L7/00

    CPC分类号： H04L7/002

    摘要： A light communication system, receiver, and method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received at the receiver. The method includes: receiving a data input stream at a receiver, the data input stream having a first data rate that is set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave so as to match the frequency of the generated wave to the transmitter clock rate of the data input stream; and using the synchronized clock rate to decode the data input stream so as to obtain data encoded in the data input stream.

    INFORMATION PROCESSING APPARATUS, SYNCHRONIZATION CORRECTION METHOD AND COMPUTER PROGRAM
    15.
    发明申请
    INFORMATION PROCESSING APPARATUS, SYNCHRONIZATION CORRECTION METHOD AND COMPUTER PROGRAM 有权
    信息处理设备，同步校正方法和计算机程序

    公开(公告)号：US20170033917A1

    公开(公告)日：2017-02-02

    申请号：US15291931

    申请日：2016-10-12

    申请人： Sony Corporation

    发明人： Seiji Ohbi

    IPC分类号： H04L7/00 ,  H04L29/06

    CPC分类号： H04L7/002 ,  H04L67/42 ,  H04N5/765 ,  H04N21/234318 ,  H04N21/4302 ,  H04N21/4307 ,  H04N21/43615

    摘要： An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.

    摘要翻译： 提供了一种信息处理装置，其包括：发送单元，用于发送用于查询另一设备的查询请求，以获得由其他设备保存的计数值;接收单元，用于从该另一设备接收计数值的返回;校正单元， 基于所接收的计数值，在预定的时间段执行用于使采样频率与这种其他设备同步的校正处理，以及用于基于采样频率与这种其他设备同步再现内容的再现单元。 校正单元通过考虑在查询请求的发送和返回的接收之间的往返时间以及在先前校正时间发生的残差而进行校正。

    Data reception apparatus oversampling received bits and data communication system oversampling received bits
    16.
    发明授权
    Data reception apparatus oversampling received bits and data communication system oversampling received bits 有权
    数据接收装置对采样的接收比特和数据通信系统进行过采样接收的比特

    公开(公告)号：US09166772B2

    公开(公告)日：2015-10-20

    申请号：US14537969

    申请日：2014-11-11

    申请人： DENSO CORPORATION

    发明人： Hironobu Akita ,  Nobuaki Matsudaira ,  Hirofumi Yamamoto

    IPC分类号： H04L7/033 ,  H04L7/00 ,  G11C27/02 ,  H04L7/04

    CPC分类号： H04L7/0087 ,  G11C27/02 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0331 ,  H04L7/0337 ,  H04L7/0338 ,  H04L7/046

    摘要： A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).

    摘要翻译： 数据接收装置通过对比特串的比特数进行积分来获得积分的比特数，通过对通过对每个比特进行过采样而获得的样本数的积分来获得积分的样本数，获得表示积分数 的比特和积分的样本数量，基于近似线，确定对应于在综合采样数之后的过采样数据中相同值继续的段的比特串的比特长度。 即使当接收侧时钟源对发送侧时钟源具有一定程度的时钟频率误差时，也可以以高于过采样周期（数字的倒数）的精度获得比特串对应的一位的多少个样本 的样品）。

    Polar transmitter having digital processing block used for adjusting frequency modulating signal for frequency deviation of frequency modulated clock and related method thereof
    17.
    发明授权
    Polar transmitter having digital processing block used for adjusting frequency modulating signal for frequency deviation of frequency modulated clock and related method thereof 有权
    具有数字处理块的极性发射机，用于调频频调制频率的频率调制信号及其相关方法

    公开(公告)号：US08804874B2

    公开(公告)日：2014-08-12

    申请号：US13612796

    申请日：2012-09-12

    申请人： Chi-Hsueh Wang ,  Kai-Peng Kao ,  Robert Bogdan Staszewski

    发明人： Chi-Hsueh Wang ,  Kai-Peng Kao ,  Robert Bogdan Staszewski

    IPC分类号： H03C3/00

    CPC分类号： H03C5/00 ,  H04L7/002 ,  H04L7/0331

    摘要： A polar transmitter includes a frequency modulating path, a clock divider and a digital processing block. The frequency modulating path is arranged for generating a frequency modulated clock in response to a frequency modulating signal. The clock divider is coupled to the frequency modulated clock, and arranged for generating a down-divided clock. The digital processing block is coupled to the down-divided clock, and arranged for generating the frequency modulating signal, wherein the frequency modulating signal is adjusted for frequency deviation of the frequency modulated clock. A method for polar transmission includes: generating a frequency modulated clock in response to a frequency modulating signal; dividing a frequency of said frequency modulated clock to generate a down-divided clock; and generating said frequency modulating signal according to said down-divided clock, wherein said frequency modulating signal is adjusted for frequency deviation of said frequency modulated clock.

    摘要翻译： 极性发射机包括频率调制路径，时钟分频器和数字处理模块。 频率调制路径被布置成响应于频率调制信号而产生调频时钟。 时钟分频器耦合到频率调制时钟，并且被布置用于产生分频时钟。 数字处理块耦合到分频时钟，并且被配置为产生频率调制信号，其中调频信号针对频率调制时钟的频率偏差。 一种用于极性传输的方法包括：响应于频率调制信号产生调频时钟; 将所述调频时钟的频率除以产生下降时钟; 以及根据所述分频时钟产生所述频率调制信号，其中调节所述频率调制信号以调节所述频率调制时钟的频率偏差。

    QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES
    18.
    发明申请
    QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES 有权
    QUASI-DIGITAL接收器用于高速伺服系统

    公开(公告)号：US20140146922A1

    公开(公告)日：2014-05-29

    申请号：US13720623

    申请日：2012-12-19

    申请人： BROADCOM CORPORATION

    发明人： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

    IPC分类号： H04L25/02

    CPC分类号： H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

    摘要： Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

    摘要翻译： 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

    Crosstalk cancellation for a multiport ethernet system
    19.
    发明授权
    Crosstalk cancellation for a multiport ethernet system 有权
    多端口以太网系统的串扰消除

    公开(公告)号：US08659986B1

    公开(公告)日：2014-02-25

    申请号：US13190419

    申请日：2011-07-25

    申请人： Jerry Martinson ,  Paul Langner ,  Hossein Sedarat

    发明人： Jerry Martinson ,  Paul Langner ,  Hossein Sedarat

    IPC分类号： H04J3/10

    CPC分类号： H04J3/0697 ,  H04B3/32 ,  H04J3/10 ,  H04L7/002

    摘要： A transceiver system is disclosed. The transceiver system comprises a first transceiver physical layer circuit (PHY) having a first plurality of channels and a second transceiver PHY disposed adjacent the first transceiver PHY and having a second plurality of channels. Filter circuitry is coupled between at least one of the plurality of first channels and at least one of the plurality of second channels.

    摘要翻译： 公开了一种收发机系统。 收发机系统包括具有第一多个信道的第一收发器物理层电路（PHY）和邻近第一收发器PHY设置并且具有第二多个信道的第二收发器PHY。 滤波器电路耦合在多个第一通道中的至少一个和多个第二通道中的至少一个之间。