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    Integrated Clock Architecture for Improved Testing
    12.
    发明申请
    Integrated Clock Architecture for Improved Testing 有权
    集成时钟架构，用于改进测试

    公开(公告)号：US20140289550A1

    公开(公告)日：2014-09-25

    申请号：US13863656

    申请日：2013-04-16

    Applicant: LSI CORPORATION

    Inventor： Ramesh C. Tekumalla ,  Vijay Sharma

    IPC: G06F1/12

    CPC classification number: G11C29/12015 ,  G01R31/318552 ,  G06F1/12 ,  G11C2029/3202

    Abstract: A computer system includes a first on-chip controller and a second on-chip controller, both connected to a control element. In normal operation, the first and second on-chip controllers operate in different clock domains. During testing, the control element causes each on-chip controller to generate a substantially similar clock signal. The substantially similar clock signals are used to test substantially similar test circuitry connected to each on-chip controller, thereby reducing overhead associated with testing. A delay may be incorporated into the path of the clock signal of one of the on-chip controllers to reduce instantaneous power draw during testing.

    Abstract translation: 计算机系统包括连接到控制元件的第一片上控制器和第二片上控制器。 在正常操作中，第一和第二片上控制器在不同的时钟域中工作。 在测试期间，控制元件使每个片上控制器产生基本相似的时钟信号。 基本类似的时钟信号用于测试连接到每个片上控制器的基本相似的测试电路，从而减少与测试相关的开销。 延迟可以并入片上控制器之一的时钟信号的路径中以减少测试期间的瞬时功率消耗。

    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    15.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
    非易失性半导体存储器件

    公开(公告)号：US20120198297A1

    公开(公告)日：2012-08-02

    申请号：US13237291

    申请日：2011-09-20

    Applicant: Takeshi KAMIGAICHI ,  Kenji Sawamura

    Inventor： Takeshi KAMIGAICHI ,  Kenji Sawamura

    IPC: G11C16/02 ,  G06F11/07

    CPC classification number: G11C11/5628 ,  G06F1/305 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/3202

    Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.

    Abstract translation: 控制电路通过对所选择的字线施加写脉冲电压，对所选字线对1页存储单元执行写操作，然后执行确认数据写入是否完成的验证读操作。 当数据写入未完成时，通过一定的升压电压来提高写入脉冲电压的升压动作。 位扫描电路根据读出放大器电路中保持的读取数据，确定在同时读取的存储单元中确定达到一定阈值电压的存储单元数是否等于或大于一定数量 的验证读取操作。 控制电路根据位扫描电路的判定来改变升压电压的量。

    Testing embedded memories in an integrated circuit
    16.
    发明授权
    Testing embedded memories in an integrated circuit 有权
    在集成电路中测试嵌入式存储器

    公开(公告)号：US08209572B2

    公开(公告)日：2012-06-26

    申请号：US12941404

    申请日：2010-11-08

    Applicant: Don E. Ross ,  Xiaogang Du ,  Wu-Tung Cheng ,  Joseph C. Rayhawk

    Inventor： Don E. Ross ,  Xiaogang Du ,  Wu-Tung Cheng ,  Joseph C. Rayhawk

    IPC: G06F17/50 ,  G11C29/00 ,  G01R31/28

    CPC classification number: G11C29/1201 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/3202

    Abstract: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.

    Abstract translation: 公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。 所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。 该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。 本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。 在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。 在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

    At-speed scan testing of memory arrays
    18.
    发明授权
    At-speed scan testing of memory arrays 有权
    存储器阵列的高速扫描测试

    公开(公告)号：US08065572B2

    公开(公告)日：2011-11-22

    申请号：US12495158

    申请日：2009-06-30

    Applicant: Thomas A. Ziaja ,  Murali Gala ,  Paul J. Dickinson ,  Karl P. Dahlgren ,  David L. Curwen ,  Oliver Caty ,  Steven C. Krow-Lucal ,  James C. Hunt ,  Poh-Joo Tan

    Inventor： Thomas A. Ziaja ,  Murali Gala ,  Paul J. Dickinson ,  Karl P. Dahlgren ,  David L. Curwen ,  Oliver Caty ,  Steven C. Krow-Lucal ,  James C. Hunt ,  Poh-Joo Tan

    IPC: G11C29/00 ,  G01R31/28

    CPC classification number: G11C29/32 ,  G01R31/318541 ,  G11C29/50012 ,  G11C2029/3202

    Abstract: An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

    Abstract translation: 一种被配置用于对存储器阵列进行高速扫描测试的集成电路。 集成电路包括具有多个串联扫描元件的扫描链，其中多个扫描元件的子集被耦合以向存储器阵列提供信号。 多个扫描元件的子集的每个扫描元件包括具有数据输入的触发器和耦合到存储器阵列的对应输入的数据输出，以及被配置为在操作模式下耦合数据路径的选择电路 并且还被配置为以扫描模式耦合到数据输入中的一个扫描输入，数据输出和数据输出的补码。 该子集的扫描元件支持与其耦合的存储器阵列的高速测试。

    System in package with built-in test-facilitating circuit
    19.
    发明授权
    System in package with built-in test-facilitating circuit 有权
    系统封装内置测试便利电路

    公开(公告)号：US08040148B2

    公开(公告)日：2011-10-18

    申请号：US12092238

    申请日：2005-11-02

    Applicant: Masayuki Satoh

    Inventor： Masayuki Satoh

    IPC: G01R31/02 ,  H01L21/48 ,  H01L23/498

    CPC classification number: G01R31/2818 ,  G01R31/2884 ,  G01R31/318533 ,  G11C29/40 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2029/3202 ,  G11C2029/5602 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: This invention relates to a system in package including a plurality of integrated circuit chips and a substrate on which the plurality of integrated circuit chips are mounted and characterized in that a testability circuit for facilitating a test on at least one of the integrated circuit chips is incorporated into the substrate. The testability circuit incorporated into the substrate is formed by embedding a so-called WLCSP integrated circuit chip into the substrate. Alternatively, the testability circuit is formed by using a transistor element formed by using a semiconductor layer formed on the substrate. By incorporating the testability circuit into the substrate as described above, it is possible to realize a system in package facilitated in test without increases in size and cost.

    Abstract translation: 本发明涉及包括多个集成电路芯片的多个集成电路芯片和其上安装有多个集成电路芯片的基板的系统，其特征在于，包括用于促进至少一个集成电路芯片的测试的可测试性电路 进入基板。 通过将所谓的WLCSP集成电路芯片嵌入到基板中来形成结合到基板中的可测试性电路。 或者，通过使用通过使用形成在基板上的半导体层形成的晶体管元件来形成可测试性电路。 通过将可测试性电路并入到基板中，可以在不增加尺寸和成本的情况下实现测试中促进的封装体系。

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