公开(公告)号：US08432194B2

公开(公告)日：2013-04-30

申请号：US12909162

申请日：2010-10-21

申请人： Tsuguto Maruko ,  Kouhei Tanaka

发明人： Tsuguto Maruko ,  Kouhei Tanaka

IPC分类号： H03B28/00

CPC分类号： H02M1/36 ,  H02M1/08

摘要： A bias potential generating circuit includes a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ΔΣ conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.

摘要翻译： 偏置电位产生电路包括产生具有预定频率的时钟信号的时钟供应电路; 上升正弦波产生电路，其生成具有正弦波上升部分的波形的上升波形信号; DeltaSigma转换电路，通过脉冲宽度调制上升波形信号产生脉宽调制信号; 第一电阻器，一端连接到运算放大器的参考电位输入端; 第二电阻器，一端连接到第一电阻器和运算放大器的参考电位输入端子，另一端接地; 以及连接到电源和第一电阻的另一端的开关，开关由脉宽调制信号导通和截止。

公开(公告)号：US08432176B2

公开(公告)日：2013-04-30

申请号：US12702347

申请日：2010-02-09

申请人： Katsuhiro Gunji ,  Toru Iwasaki ,  Takaaki Sasaki

发明人： Katsuhiro Gunji ,  Toru Iwasaki ,  Takaaki Sasaki

IPC分类号： G01R31/00

CPC分类号： G01R31/2865 ,  G01R31/2875

摘要： A test apparatus for testing semiconductor integrated circuits includes a test head, a probe card holder for detachably holding a probe card that probes a semiconductor device, a heater for heating the probe card, and a heater holder that holds the heater in direct contact with the probe card when the probe card is held by the probe card holder. The test apparatus heats the probe card efficiently and thereby reduces test time and cost.

摘要翻译： 用于测试半导体集成电路的测试装置包括测试头，用于可拆卸地保持探测半导体器件的探针卡的探针卡保持器，用于加热探针卡的加热器和将加热器保持在与 当探头卡被探头卡夹固定时，探针卡。 测试装置有效地加热探针卡，从而减少测试时间和成本。

公开(公告)号：US08421136B2

公开(公告)日：2013-04-16

申请号：US12511253

申请日：2009-07-29

申请人： Kenichirou Sugio ,  Kenichirou Tanaka

发明人： Kenichirou Sugio ,  Kenichirou Tanaka

IPC分类号： H01L27/146

CPC分类号： H01L27/14 ,  H01L23/552 ,  H01L27/14623 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device that includes a circuit portion, a first light-shielding film and plural second light-shielding films. In the circuit portion, a plurality of wiring layers that include circuit elements are laminated. The first light-shielding film covers an uppermost layer of the wiring layers and light-shields light that is illuminated at the circuit portion. The second light-shielding films are covered by the first light shielding film and formed so as to respectively encircle the wiring layers in ring forms. Outer peripheries of the plural second light-shielding films are formed to be successively smaller from an upper to a lower layer, so as to be at the inner side relative to the outer periphery of the second light-shielding film of the upper layer.

摘要翻译： 一种半导体器件，包括电路部分，第一遮光膜和多个第二光屏蔽膜。 在电路部分中，层叠包括电路元件的多个布线层。 第一遮光膜覆盖布线层的最上层，并对在电路部分照明的光进行遮光。 第二遮光膜被第一遮光膜覆盖，并形成为以环状分别环绕布线层。 多个第二遮光膜的外周形成为从上层到下层相对较小地相对于上层的第二遮光膜的外周的内侧。

公开(公告)号：US08412277B2

公开(公告)日：2013-04-02

申请号：US12591432

申请日：2009-11-19

申请人： Kazunori Fujiwara

发明人： Kazunori Fujiwara

IPC分类号： H04M1/00 ,  H04B1/38

CPC分类号： G01V7/02 ,  G01V7/04 ,  G06F1/1626 ,  G06F1/1694 ,  G06F2200/1614 ,  G06F2200/1637 ,  H04M2250/12

摘要： A gravity axis determination apparatus which can determine the gravity direction in a short time. The apparatus is low in cost and has a simple construction. Data values of acceleration data trains in a same time zone are mutually compared and one of the three axes is determined as a gravity axis.

公开(公告)号：US08408859B2

公开(公告)日：2013-04-02

申请号：US12356672

申请日：2009-01-21

申请人： Katsuhiro Yoshino

发明人： Katsuhiro Yoshino

IPC分类号： B65H1/00

CPC分类号： H01L21/67781 ,  H01L21/67766

摘要： A wafer transfer device and method capable of preventing a wafer from falling off of a carrier. A first carrier receiver holding a first carrier has a box-like shape having an opening through which the first carrier is attached/removed to/from the first carrier receiving member. A second carrier receiver holding a second carrier has a box-like shape having an opening through which the second carrier is attached/removed to/from the first carrier receiving member. The first carrier and the second carrier can be attached/removed to/from the first carrier receiver and the second carrier receiver, respectively. Owing to such a configuration, it is possible to prevent a wafer received in the first carrier and the second carrier from falling off from the first carrier and the second carrier, respectively.

摘要翻译： 一种能够防止晶片从载体上脱落的晶片转移装置和方法。 保持第一载体的第一载体接收器具有盒形形状，其具有开口，第一载体通过该开口与第一载体接收构件相连/去除。 保持第二载体的第二载体接收器具有盒形形状，其具有开口，第二载体通过该开口被附接到第一载体接收构件或从第一载体接收构件移除。 第一载波和第二载波可以分别附接/去除第一载波接收机和第二载波接收机。 由于这样的结构，可以防止在第一载体和第二载体中接收的晶片分别从第一载体和第二载体脱落。

公开(公告)号：US08405783B2

公开(公告)日：2013-03-26

申请号：US12272099

申请日：2008-11-17

申请人： Takashi Taya

发明人： Takashi Taya

IPC分类号： H04N5/44 ,  H04N5/63

CPC分类号： H04N5/4403 ,  G08C17/00 ,  H04N5/63 ,  H04N21/42202 ,  H04N21/42222 ,  H04N21/4334 ,  H04N21/4436 ,  H04N2005/4428

摘要： An electronic device includes a wireless receiving circuit for receiving signals transmitted from a remote control unit, a core circuit having a digital signal processing circuit for processing input signals and configured to perform at least one of display processing and record processing based on signals processed in the digital signal processing circuit in accordance with a control signal transmitted from the remote control unit and received by the wireless receiving circuit, and a preliminary activation circuit for starting electric power supply to the digital signal processing circuit to thereby activate the digital signal processing circuit when a pre-operation state where the remote control unit is expected to be operated during stoppage of electric power supply to the core circuit has occurred.

摘要翻译： 电子设备包括用于接收从遥控单元发送的信号的无线接收电路，具有用于处理输入信号的数字信号处理电路的核心电路，并且被配置为基于处理输入信号中的信号执行显示处理和记录处理中的至少一个 数字信号处理电路，根据从遥控单元发送并由无线接收电路接收的控制信号;以及预备激活电路，用于向数字信号处理电路启动电力供应，从而当数字信号处理电路 发生了在停止向核心电路供电的情况下遥控单元预期运行的预运行状态。

公开(公告)号：US08405459B2

公开(公告)日：2013-03-26

申请号：US13064935

申请日：2011-04-27

申请人： Tetsuji Maruyama

发明人： Tetsuji Maruyama

IPC分类号： H03F3/45

CPC分类号： H03F3/45192

摘要： A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.

摘要翻译： 折叠共源共栅差分放大器包括高压输入级和低压输出级。 输入级由高压MOS晶体管形成，其中两个构成差分对。 输出级由低压MOS晶体管形成，其中一些构成连接到差分对的电流镜电路。 输出级还包括放大电流镜电路中产生的电压以产生输出电压信号的至少一个晶体管。 高压MOS晶体管具有比低压MOS晶体管更高的击穿电压。 将两种类型的晶体管结合到单个放大器中减少必要数量的晶体管和必要数量的偏置电压。

公开(公告)号：US08399950B2

公开(公告)日：2013-03-19

申请号：US13047934

申请日：2011-03-15

申请人： Noriyuki Miura

发明人： Noriyuki Miura

IPC分类号： H01L31/0232

CPC分类号： H01L27/1443 ,  H01L31/105

摘要： A photodiode includes a photosensitive element formed in a silicon semiconductor layer on an insulation layer. The photosensitive element includes a low concentration diffusion layer, a P-type high concentration diffusion layer, and an N-type high concentration diffusion layer. A method of producing the photodiode includes the steps of: forming an insulation material layer on the silicon semiconductor layer after the P-type impurity and the N-type impurity are implanted into the low concentration diffusion layer, the P-type high concentration diffusion layer, and the N-type high concentration diffusion layer; forming an opening portion in the insulation material layer in an area for forming the low concentration diffusion layer; and etching the silicon semiconductor layer in the area for forming the low concentration diffusion layer so that a thickness of the silicon semiconductor layer is reduced to a specific level.

摘要翻译： 光电二极管包括形成在绝缘层上的硅半导体层中的感光元件。 感光元件包括低浓度扩散层，P型高浓度扩散层和N型高浓度扩散层。 制造光电二极管的方法包括以下步骤：在P型杂质和N型杂质注入低浓度扩散层之后，在硅半导体层上形成绝缘材料层，P型高浓度扩散层 ，和N型高浓度扩散层; 在用于形成低浓度扩散层的区域中在绝缘材料层中形成开口部分; 并且在用于形成低浓度扩散层的区域中蚀刻硅半导体层，使得硅半导体层的厚度降低到特定的水平。

公开(公告)号：US08399351B2

公开(公告)日：2013-03-19

申请号：US12659600

申请日：2010-03-15

申请人： Masashi Takahashi

发明人： Masashi Takahashi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/28556

摘要： A semiconductor device manufacturing method includes a process for filling holes in a dielectric film with tungsten. The process deposits tungsten in the holes, partially etches the deposited tungsten, and then deposits additional tungsten in the holes. Voids that may be left by the first tungsten deposition step are made accessible by openings formed in the etching step, and are then filled in by the second tungsten deposition step. Tungsten hexafluoride may be used as both a deposition source gas and an etching gas, providing a simple and inexpensive process that is suitable for high-volume production.

摘要翻译： 半导体器件制造方法包括用钨填充电介质膜中的孔的工艺。 该过程在孔中沉积钨，部分蚀刻沉积的钨，然后在孔中沉积额外的钨。 可以通过第一钨沉积步骤留下的空隙使得可以通过在蚀刻步骤中形成的开口来访问，然后通过第二钨沉积步骤填充。 六氟化钨可用作沉积源气体和蚀刻气体，提供适合于大批量生产的简单且便宜的方法。

公开(公告)号：US08329591B2

公开(公告)日：2012-12-11

申请号：US12101334

申请日：2008-04-11

申请人： Shinji Kawada

发明人： Shinji Kawada

IPC分类号： H01L21/3065

CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76805

摘要： Disclosed is a means for stabilizing quality of a semiconductor device by preventing projections from being formed in the bottom of a through hole. A method of manufacturing a semiconductor device includes a process of forming a through hole reaching a metal nitride layer through an interlayer insulating layer on a semiconductor wafer on which the wiring layer, the metal nitride layer formed on the wiring layer, and the interlayer insulating layer covering the wiring layer and the metal nitride layer are formed. The through hole forming process includes: a first etching step of etching the interlayer insulating layer by an anisotropic etching method with the semiconductor wafer set to a first temperature; and a second etching step of etching an upper surface of metal nitride layer by an anisotropic etching method with the semiconductor wafer set to a second temperature higher than the first temperature.

摘要翻译： 公开了一种通过防止在通孔的底部形成突起来稳定半导体器件的质量的手段。 一种制造半导体器件的方法包括：在半导体晶片上形成通过层间绝缘层到达金属氮化物层的通孔的工艺，其中布线层，形成在布线层上的金属氮化物层和层间绝缘层 覆盖布线层和金属氮化物层。 通孔形成工艺包括：第一蚀刻步骤，通过使半导体晶片设定为第一温度的各向异性蚀刻方法蚀刻层间绝缘层; 以及第二蚀刻步骤，通过各向异性蚀刻方法蚀刻金属氮化物层的上表面，半导体晶片设置为高于第一温度的第二温度。