公开(公告)号：US20110095793A1

公开(公告)日：2011-04-28

申请号：US12909162

申请日：2010-10-21

申请人： Tsuguto Maruko ,  Kouhei Tanaka

发明人： Tsuguto Maruko ,  Kouhei Tanaka

IPC分类号： H03B28/00

CPC分类号： H02M1/36 ,  H02M1/08

摘要： The present invention provides a bias potential generating circuit including: a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ΔΣ conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.

摘要翻译： 本发明提供了一种偏置电位发生电路，包括：时钟供给电路，生成具有预定频率的时钟信号; 上升正弦波产生电路，其生成具有正弦波上升部分的波形的上升波形信号; a＆Dgr＆＆ 转换电路，通过脉冲宽度调制上升波形信号产生脉宽调制信号; 第一电阻器，一端连接到运算放大器的参考电位输入端; 第二电阻器，一端连接到第一电阻器和运算放大器的参考电位输入端子，另一端接地; 以及连接到电源和第一电阻的另一端的开关，开关由脉宽调制信号导通和截止。

公开(公告)号：US20090016543A1

公开(公告)日：2009-01-15

申请号：US12123751

申请日：2008-05-20

申请人： Tsuguto MARUKO ,  Naotaka SAITO

发明人： Tsuguto MARUKO ,  Naotaka SAITO

IPC分类号： H03G3/00

CPC分类号： H04R3/04

摘要： An apparatus for performing processing of an input acoustic signal to be reproduced by a loudspeaker, which generates a harmonic of a low pitch sound component equal to or lower than a predetermined low cutoff frequency, and generates a harmonic synthesized acoustic signal synthesizing the input signal with the harmonic. The apparatus generates an output acoustic signal which cuts off, from the harmonic synthesized acoustic signal, a low pitch sound component equal to or lower than the low cutoff frequency and a high pitch sound component equal to or higher than the high cutoff frequency. The apparatus sets a low and high cutoff frequencies in accordance with an output characteristic of a loudspeaker.

摘要翻译： 一种用于执行要由扬声器再现的输入声信号的处理的装置，其产生等于或低于预定低截止频率的低音高音分量的谐波，并且产生合成输入信号的谐波合成声信号， 谐波。 该装置产生输出声信号，其从谐波合成声信号中切断等于或低于低截止频率的低音高音分量和等于或高于高截止频率的高音调声分量。 该装置根据扬声器的输出特性设置低和高截止频率。

公开(公告)号：US07557604B2

公开(公告)日：2009-07-07

申请号：US11119899

申请日：2005-05-03

申请人： Shinsuke Onishi ,  Tsuguto Maruko

发明人： Shinsuke Onishi ,  Tsuguto Maruko

IPC分类号： H03K19/177

CPC分类号： H03K19/1732

摘要： An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status at the mode setting terminal; and a control circuit that controls the logic holding circuit in accordance with a signal supplied to the chip selection terminal. Operation modes to be selected may be serial interface mode and parallel interface mode.

摘要翻译： 一种用于模式设置的输入电路，包括：芯片选择端子，其可在第一和第二操作模式中操作; 用于从第一和第二操作模式之间选择操作模式的模式设置终端; 逻辑保持电路，在模式设定端子保持逻辑状态; 以及根据提供给芯片选择端的信号来控制逻辑保持电路的控制电路。 要选择的操作模式可以是串行接口模式和并行接口模式。

公开(公告)号：US20060279325A1

公开(公告)日：2006-12-14

申请号：US11119899

申请日：2005-05-03

申请人： Shinsuke Onishi ,  Tsuguto Maruko

发明人： Shinsuke Onishi ,  Tsuguto Maruko

IPC分类号： H03K19/173

CPC分类号： H03K19/1732

摘要： An input circuit for mode setting, comprising: a chip selection terminal that is operable both in first and second operation modes; a mode setting terminal that is used to select an operation mode from between the first and second operation modes; a logic holding circuit that holds a logic status at the mode setting terminal; and a control circuit that controls the logic holding circuit in accordance with a signal supplied to the chip selection terminal. Operation modes to be selected may be serial interface mode and parallel interface mode.

公开(公告)号：US08495270B2

公开(公告)日：2013-07-23

申请号：US13159531

申请日：2011-06-14

申请人： Tsuguto Maruko

发明人： Tsuguto Maruko

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F1/10

摘要： A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal. In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal.

摘要翻译： 通信接口装置包括：第一接口电路，包括连接到第一终端的芯片选择终端，连接到第二终端的时钟终端和连接到第三终端的数据终端; 以及包括连接到第一终端的第二时钟终端和连接到第三终端的数据终端的第二接口电路。 在通过第一接口电路执行通信的情况下，将固定在预定电平的固定信号输入到第一终端中，时钟信号被输入到第二终端，数据信号被输入到第三终端 通过第二接口电路执行通信的情况下，将时钟信号输入到第一端子，并将数据信号输入到第三端子。

公开(公告)号：US08432194B2

公开(公告)日：2013-04-30

申请号：US12909162

申请日：2010-10-21

申请人： Tsuguto Maruko ,  Kouhei Tanaka

发明人： Tsuguto Maruko ,  Kouhei Tanaka

IPC分类号： H03B28/00

CPC分类号： H02M1/36 ,  H02M1/08

摘要： A bias potential generating circuit includes a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ΔΣ conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.

摘要翻译： 偏置电位产生电路包括产生具有预定频率的时钟信号的时钟供应电路; 上升正弦波产生电路，其生成具有正弦波上升部分的波形的上升波形信号; DeltaSigma转换电路，通过脉冲宽度调制上升波形信号产生脉宽调制信号; 第一电阻器，一端连接到运算放大器的参考电位输入端; 第二电阻器，一端连接到第一电阻器和运算放大器的参考电位输入端子，另一端接地; 以及连接到电源和第一电阻的另一端的开关，开关由脉宽调制信号导通和截止。

公开(公告)号：US08103010B2

公开(公告)日：2012-01-24

申请号：US12123751

申请日：2008-05-20

申请人： Tsuguto Maruko ,  Naotaka Saito

发明人： Tsuguto Maruko ,  Naotaka Saito

IPC分类号： H03G3/00

CPC分类号： H04R3/04

摘要： An apparatus for performing processing of an input acoustic signal to be reproduced by a loudspeaker, which generates a harmonic of a low pitch sound component equal to or lower than a predetermined low cutoff frequency, and generates a harmonic synthesized acoustic signal synthesizing the input signal with the harmonic. The apparatus generates an output acoustic signal which cuts off, from the harmonic synthesized acoustic signal, a low pitch sound component equal to or lower than the low cutoff frequency and a high pitch sound component equal to or higher than the high cutoff frequency. The apparatus sets a low and high cutoff frequencies in accordance with an output characteristic of a loudspeaker.

摘要翻译： 一种用于执行要由扬声器再现的输入声信号的处理的装置，其产生等于或低于预定低截止频率的低音高音分量的谐波，并且产生合成输入信号的谐波合成声信号， 谐波。 该装置产生输出声信号，其从谐波合成声信号中切断等于或低于低截止频率的低音高音分量和等于或高于高截止频率的高音调声分量。 该装置根据扬声器的输出特性设置低和高截止频率。

公开(公告)号：US20110320853A1

公开(公告)日：2011-12-29

申请号：US13159531

申请日：2011-06-14

申请人： Tsuguto Maruko

发明人： Tsuguto Maruko

IPC分类号： G06F1/12

CPC分类号： G06F1/10

摘要： A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal

摘要翻译： 通信接口装置包括：第一接口电路，包括连接到第一终端的芯片选择终端，连接到第二终端的时钟终端和连接到第三终端的数据终端; 以及第二接口电路，包括连接到第一终端的第二时钟端子和连接到第三端子的数据端子。在由第一接口电路进行通信的情况下，固定在预定电平的固定信号被输入到第一端子 时钟信号被输入到第二终端，并且数据信号被输入到第三终端中，并且在通过第二接口电路执行通信的情况下，时钟信号被输入到第一终端，并且数据信号被输入 进入第三个终端

公开(公告)号：US07924190B2

公开(公告)日：2011-04-12

申请号：US12562645

申请日：2009-09-18

申请人： Tsuguto Maruko ,  Naotaka Saito

发明人： Tsuguto Maruko ,  Naotaka Saito

IPC分类号： H03M1/00

CPC分类号： H03M1/185 ,  H03G3/001 ,  H03M1/504

摘要： A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.

摘要翻译： 数字ALC的CLK产生部分产生通过将在三角波发生电路处产生的三角波乘以而获得的乘法时钟信号。 基于乘法时钟信号，信号转换部将从输出级输出的1位数字音频信号转换为多位数字信号，并监视输入信号的电压值。 电平控制部根据从LSI的外部输入的目标电平来控制电压电平。 基于从LSI的外部输入的控制信号，音量控制部分向PGA输出增益调整信号，以改变输入信号的波形。

公开(公告)号：US20100073213A1

公开(公告)日：2010-03-25

申请号：US12562645

申请日：2009-09-18

申请人： Tsuguto Maruko ,  Naotaka Saito

发明人： Tsuguto Maruko ,  Naotaka Saito

IPC分类号： H03M1/12

CPC分类号： H03M1/185 ,  H03G3/001 ,  H03M1/504

摘要： A CLK generating section of a digital ALC generates a multiplication clock signal that is obtained by multiplying a triangular wave generated at a triangular wave generating circuit. On the basis of the multiplication clock signal, a signal converting section converts a one-bit digital audio signal outputted from an outputting stage into a multi-bit digital signal, and monitors a voltage value of an input signal. A level controlling section controls a voltage level on the basis of a target level inputted from an exterior of an LSI. On the basis of a control signal inputted from an exterior of the LSI, a volume controlling section outputs, to a PGA, a gain adjusting signal so as to vary a waveform of an input signal.

摘要翻译： 数字ALC的CLK产生部分产生通过将在三角波发生电路处产生的三角波乘以而获得的乘法时钟信号。 基于乘法时钟信号，信号转换部将从输出级输出的1位数字音频信号转换为多位数字信号，并监视输入信号的电压值。 电平控制部根据从LSI的外部输入的目标电平来控制电压电平。 基于从LSI的外部输入的控制信号，音量控制部分向PGA输出增益调整信号，以改变输入信号的波形。