公开(公告)号：US07149131B2

公开(公告)日：2006-12-12

申请号：US11024969

申请日：2004-12-30

Applicant: Jun-Gi Choi ,  Yong-Kyu Kim

Inventor： Jun-Gi Choi ,  Yong-Kyu Kim

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4074 ,  G11C5/147

Abstract: A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.

Abstract translation: 半导体存储器件通过保持内部电源电压和核心电压的质量来降低功耗。 半导体存储器件在预充电期间充分保持核心电压来降低功耗。 该半导体存储装置包括接收外部控制信号以输出有效信号和预充电信号的指令解码器，接收有效信号的内部电源电压产生控制单元和用于激活内部电力电压有源信号预定时间的预充电信号， 接收有效信号的核心电压产生控制单元，用于激活核心电压有源信号预定时间的预充电信号和内部电源电压有效信号;内部电源电压产生单元，用于在激活期间内产生内部电源电压 内部电源电压有效信号; 以及核心电压产生单元，用于在核心电压有源信号的激活期间产生核心电压。

公开(公告)号：US20060092743A1

公开(公告)日：2006-05-04

申请号：US11024969

申请日：2004-12-30

Applicant: Jun-Gi Choi ,  Yong-Kyu Kim

Inventor： Jun-Gi Choi ,  Yong-Kyu Kim

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C11/4074 ,  G11C5/147

Abstract: A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge. The semiconductor memory device includes a command decoder receiving external control signals to output an active signal and a precharge signal, an internal power voltage generation controlling unit receiving the active signal and the precharge signal for activating an internal power voltage active signal for a predetermined time, a core voltage generation controlling unit receiving the active signal, the precharge signal and the internal power voltage active signal for activating a core voltage active signal for a predetermined time, an internal power voltage generating unit for generating an internal power voltage during the activation period of the internal power voltage active signal; and a core voltage generating unit for generating a core voltage during the activation period of the core voltage active signal.

公开(公告)号：US20060050589A1

公开(公告)日：2006-03-09

申请号：US11020244

申请日：2004-12-27

Applicant: Jun-Gi Choi ,  Yong-Kyu Kim

Inventor： Jun-Gi Choi ,  Yong-Kyu Kim

IPC: G11C5/14

CPC classification number: G11C8/08 ,  G11C5/147

Abstract: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.

Abstract translation: 本发明提供一种电源电压供应器，通过采用储层电容器的共用方案，不增加储层电容器的尺寸，稳定地提供无噪声电力电压。 半导体存储器件的电源电压供应器包括：用于提供第一电源电压的第一电源电压线; 用于提供第二电源电压的第二电源电压线; 用于稳定地提供第一和第二电源电压的第一储存电容器; 以及储存电容器控制器，用于选择性地将第一储存电容器连接到第一电源电压线或第二电源电压线。

公开(公告)号：US08120015B2

公开(公告)日：2012-02-21

申请号：US12357681

申请日：2009-01-22

Applicant: Yun-Kwon Park ,  Sung-Woo Hwang ,  Jea-Shik Shin ,  Byeoung-Ju Ha ,  Jae-Sung Rieh ,  In-Sang Song ,  Yong-Kyu Kim ,  Byeong-Kwon Ju ,  Hee-Tae Kim

Inventor： Yun-Kwon Park ,  Sung-Woo Hwang ,  Jea-Shik Shin ,  Byeoung-Ju Ha ,  Jae-Sung Rieh ,  In-Sang Song ,  Yong-Kyu Kim ,  Byeong-Kwon Ju ,  Hee-Tae Kim

IPC: H01L29/06

CPC classification number: H01L29/0665 ,  B81B2201/0271 ,  B81C1/00142 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/49 ,  H01L29/78 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.

Abstract translation: 提供了一种谐振结构，包括第一端子，面向第一端子的第二端子，连接第一端子和第二端子的导线单元，与导线单元隔开一定距离的第三端子，以及 使导线单元谐振，以及形成在导线单元上并提供负电阻分量的势垒单元。 因此，可以提高转导效率。

公开(公告)号：US07668034B2

公开(公告)日：2010-02-23

申请号：US12068273

申请日：2008-02-05

Applicant: Jun-Gi Choi ,  Yong-Kyu Kim

Inventor： Jun-Gi Choi ,  Yong-Kyu Kim

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C5/147

Abstract: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.

Abstract translation: 本发明提供一种电源电压供应器，通过采用储层电容器的共用方案，不增加储层电容器的尺寸，稳定地提供无噪声电力电压。 半导体存储器件的电源电压供应器包括：用于提供第一电源电压的第一电源电压线; 用于提供第二电源电压的第二电源电压线; 用于稳定地提供第一和第二电源电压的第一储存电容器; 以及储存电容器控制器，用于选择性地将第一储存电容器连接到第一电源电压线或第二电源电压线。

公开(公告)号：US20060278428A1

公开(公告)日：2006-12-14

申请号：US11375059

申请日：2006-03-15

Applicant: Yong-Kyu Kim

Inventor： Yong-Kyu Kim

IPC: H01B7/00

CPC classification number: H04M1/0237

Abstract: A portable terminal includes a first housing, a second housing, and a sliding module. The second housing is slidably connected to the first housing such that the second housing slides longitudinally on the first housing to open or close a face of the first housing. The sliding module is interposed between the first housing and the second housing to slidably combine the second housing to the first housing. The sliding module includes a pair of guide rods and a guide plate. The guide rods are mounted spaced apart on the rear face of the second housing along a sliding direction of the second housing. The guide plate is fixed to a face of the first housing. The guide plate is slidably connected to the guide rods.

公开(公告)号：US20060220729A1

公开(公告)日：2006-10-05

申请号：US11181008

申请日：2005-07-12

Applicant: Yong-Kyu Kim

Inventor： Yong-Kyu Kim

IPC: G05F1/10

CPC classification number: H02M3/07 ,  G11C5/143 ,  G11C5/145 ,  H02M2001/0022

Abstract: Provided is an internal voltage generator for preventing an occurrence of leakage current while a charge pumping is not performed. The internal voltage generator includes: a charge pumping unit for pumping an external voltage to generate a high voltage higher than the external voltage; a level detecting unit for detecting a level drop of the high voltage with respect to a reference voltage and outputting a detection signal; an oscillating unit for generating an oscillation signal in response to the detection signal; a pumping control signal generating unit for controlling a driving of the charge pumping unit in response to the oscillation signal; and a charge pump controlling unit for precharging the charge pumping unit in response to the detection signal.

Abstract translation: 提供一种内部电压发生器，用于在不执行电荷泵送时防止泄漏电流的发生。 内部电压发生器包括：用于泵浦外部电压以产生高于外部电压的高电压的电荷泵送单元; 电平检测单元，用于检测高电压相对于参考电压的电平降低并输出检测信号; 振荡单元，用于响应于所述检测信号产生振荡信号; 泵送控制信号产生单元，用于响应于振荡信号控制电荷泵送单元的驱动; 以及电荷泵控制单元，用于响应于检测信号对电荷泵送单元进行预充电。

公开(公告)号：US5533138A

公开(公告)日：1996-07-02

申请号：US239848

申请日：1994-05-09

Applicant: Yong-Kyu Kim ,  Tianmin Liu ,  Steven T. Jaffe ,  Christopher H. Strolle

Inventor： Yong-Kyu Kim ,  Tianmin Liu ,  Steven T. Jaffe ,  Christopher H. Strolle

IPC: H04N5/92 ,  G06T9/00 ,  H03M7/00 ,  H04N1/41 ,  H04N5/783 ,  H04N5/926 ,  H04N7/26 ,  H04N7/28 ,  H04N7/30 ,  H04N7/12 ,  G06K9/36

CPC classification number: H04N5/9264 ,  H04N19/124 ,  H04N19/14 ,  H04N19/147 ,  H04N19/15 ,  H04N19/154 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/196 ,  H04N19/60 ,  H04N19/94 ,  H04N19/146 ,  H04N5/783

Abstract: Television images to be digitally recorded are divided into blocks and the discrete cosine transform DCT of each block is taken. The DC coefficient of each DCT block is scalar-quantized, and its AC coefficients are classified-vector-quantized (CVQ). The square of the value that part or all the AC coefficients among horizontal AC coefficients including a first AC coefficient and vertical AC coefficients including a second AC coefficient, according to the zigzag scanning sequence of DCT block, are subtracted from a representative value of a preset reference class. Using a multilevel compression method, lowest level codes are vector-partitioned by P-units at equal intervals with respect to each classified DCT block, and code books of representative vectors corresponding to the partitioned vectors are provided. Indices of corresponding representative vectors in respective code books and the classified codes are taken as encoding data corresponding to AC coefficients to keep a constant number of bits in the lowest level codes. Then, errors created in a preceding level are corrected. Code books of S-units of representative vectors corresponding to the errors are provided again, and corresponding indices and parity data in the respective code books are provided. Here, codes are output in which an image is more compactly compressed in lower levels, and higher levels have more elaborate picture quality. During tape recording, the codes descriptive of the scalar quantized DC term, the classification of the AC terms and the lowest-level vector-quantization index for each successive DCT block are grouped together for recording in a respective one of regularly spaced equal-length segments of the recording tracks. Decoding is performed in the reverse sequence of encoding. During a high speed search, only lowest level codes having a constant number of bits are decoded regardless of the complexity of the picture, so that picture quality is good enough to discern the nature of the images.