公开(公告)号：US09842187B1

公开(公告)日：2017-12-12

申请号：US15082993

申请日：2016-03-28

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Atul Srinivasan ,  Ilya K. Ganusov ,  Walter A. Manaker, Jr. ,  Benjamin S. Devlin ,  Satish B. Sivaswamy

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5054 ,  G06F2217/84

Abstract: Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.

公开(公告)号：US09531351B1

公开(公告)日：2016-12-27

申请号：US14835571

申请日：2015-08-25

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Ilya K. Ganusov

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0372

Abstract: In an example implementation, a circuit includes first and second latch circuits. A circuit coupled to the first and second latch circuits is configured to provide a first clock signal to the clock input node of the second latch circuit and provide a second clock signal that is an inversion of the first clock signal to the clock input node of the first latch circuit. The circuit includes a first multiplexer having a first input node coupled to a data output node of the first latch circuit, a second input node coupled to a data input node of the first latch circuit, and an output node coupled to a data input node of the second latch circuit. The circuit also includes a second multiplexer having a first input node coupled to the data output node of the first latch circuit and a second input node coupled to a data output node of the second latch circuit.

Abstract translation: 在示例实现中，电路包括第一和第二锁存电路。 耦合到第一和第二锁存电路的电路被配置为向第二锁存电路的时钟输入节点提供第一时钟信号，并提供第二时钟信号，该第二时钟信号是将第一时钟信号反转到时钟输入节点 第一锁存电路。 电路包括第一多路复用器，其具有耦合到第一锁存电路的数据输出节点的第一输入节点，耦合到第一锁存电路的数据输入节点的第二输入节点，以及耦合到第一锁存电路的数据输入节点的输出节点 第二锁存电路。 电路还包括第二多路复用器，其具有耦合到第一锁存电路的数据输出节点的第一输入节点和耦合到第二锁存电路的数据输出节点的第二输入节点。

公开(公告)号：US20190181863A1

公开(公告)日：2019-06-13

申请号：US15836571

申请日：2017-12-08

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Brian C. Gaide ,  Henri Fraisse

IPC: H03K19/003 ,  H03K19/20 ,  H03K19/177 ,  H03K19/173 ,  H03K3/037 ,  H03K19/0175

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

公开(公告)号：US10069486B1

公开(公告)日：2018-09-04

申请号：US15196466

申请日：2016-06-29

Applicant: Xilinx, Inc.

Inventor： Benjamin S. Devlin ,  Ilya K. Ganusov

IPC: H03K3/289 ,  H03K3/3562 ,  H03K3/037

Abstract: A register circuit includes a first pulse-latch circuit configured to store data from a first input node. A multiplexer circuit is configured to select between an output of the first pulse-latch circuit and a second input node. A second pulse-latch circuit is configured to store data provided by the multiplexer circuit. A control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a dual-latch mode.

公开(公告)号：US20170161419A1

公开(公告)日：2017-06-08

申请号：US14960176

申请日：2015-12-04

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Henri Fraisse ,  Ashish Sirasao ,  Alireza S. Kaviani

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

Abstract: Disclosed approaches for processing a circuit design include identifying duplicate instances of a module in a representation of the circuit design. A processor circuit performs folding operations for at least one pair of the duplicate instances of the module. One instance of the duplicates is removed from the circuit design, and a multiplexer is inserted. The multiplexer receives and selects one of the input signals to the duplicate instances and provides the selected input signal to the remaining instance. For each flip-flop in the remaining instance, a pipelined flip-flop is inserted. Connections to a first clock signal in the remaining instance are replaced with connections to a second clock signal having twice the frequency of the first clock signal. An alignment circuit is inserted to receive the output signal from the first instance and provide concurrent first and second output signals.

公开(公告)号：US09118310B1

公开(公告)日：2015-08-25

申请号：US14482832

申请日：2014-09-10

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K19/177 ,  H03K5/14 ,  H03K5/135 ,  H03K19/173

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03K5/15006 ,  H03K5/156 ,  H03K19/1737 ,  H03K19/17748

Abstract: A programmable delay circuit block includes an input stage having a cascade input and a clock input, wherein the input stage passes a signal received at the cascade input or a signal received at the clock input. The programmable delay circuit block further may include a delay block configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage and a pulse generator configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block also includes an output stage having a cascade output and a clock output. The output stage is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output and pass the signal received at the clock input, the inverted version of the pulse signal, or the delayed signal from the clock output.

Abstract translation: 可编程延迟电路块包括具有级联输入和时钟输入的输入级，其中输入级通过在级联输入处接收的信号或在时钟输入处接收的信号。 可编程延迟电路块还可以包括延迟块，其被配置为通过对从输入级传递的信号施加选定量的延迟来产生延迟信号;以及脉冲发生器，被配置为产生脉冲信号，脉冲信号具有取决于 拖延量 可编程延迟电路块还包括具有级联输出和时钟输出的输出级。 输出级被配置为使来自级联输出的脉冲信号或延迟信号的反转版本通过，并且传递在时钟输入处接收到的信号，脉冲信号的反相形式或来自时钟输出的延迟信号。

公开(公告)号：US10340898B1

公开(公告)日：2019-07-02

申请号：US15632236

申请日：2017-06-23

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov

IPC: H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K5/135 ,  H03K19/173

Abstract: The disclosed pulsed latched circuitry includes first and second latch circuits. The first and second latch circuits can be provided with additional logic circuit components to permit them to be operated as a flip-flop circuit, or as a FIFO circuit with a depth of two.

公开(公告)号：US10230374B1

公开(公告)日：2019-03-12

申请号：US15267572

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin

IPC: H03K19/177 ,  H03K3/037 ,  G06F17/50

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits preventing hold violations in clock synchronized circuits. In an example implementation, a circuit includes a logic circuit having a set of inputs. Signal propagation time on a signal path to at least one of the set of inputs presents a hold violation. The circuit includes first and second level-sensitive latches. The first level-sensitive latch has an output connected to the one of the plurality of inputs. The second level-sensitive latch has an input connected to an output of the logic circuit. A latch control circuit is configured to remove the hold violation on the input by providing a pulsed clock signal to a clock input of the second level-sensitive latch and an inversion of the pulsed clock signal to a clock input of the first level-sensitive latch.

公开(公告)号：US09954534B2

公开(公告)日：2018-04-24

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H01L25/00 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.

公开(公告)号：US20180083633A1

公开(公告)日：2018-03-22

申请号：US15267880

申请日：2016-09-16

Applicant: Xilinx, Inc.

Inventor： Ilya K. Ganusov ,  Benjamin S. Devlin ,  Henri Fraisse

IPC: H03K19/177 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K19/1776 ,  G06F17/5072 ,  G06F17/5077 ,  H03K3/0372 ,  H03K3/0375 ,  H03K19/17728

Abstract: Aspects of various embodiments of the present disclosure are directed to methods and circuits for preventing hold time violations in clock synchronized circuits. In an example implementation, a circuit includes at least a first flip-flop, a second flip-flop, and a level-sensitive latch connected in a signal path from the first flip-flop to the second flip-flop. A clock node of the first flip-flop is connected to receive a first clock signal and a clock node of the second flip-flop is connected to receive a second clock signal. The propagation delay from the first flip-flop through the level-sensitive latch to the second flip-flop is smaller than the skew between the first clock and the second clock, thereby presenting a hold time violation. A level-sensitive latch control circuit is configured to prevent the hold time violation by providing a pulsed clock signal to a clock node of the one level-sensitive latch circuit.