Circuits for and methods of enabling the modification of an input data stream
    12.
    发明授权
    Circuits for and methods of enabling the modification of an input data stream 有权
    用于启用输入数据流修改的电路和方法

    公开(公告)号:US09235498B1

    公开(公告)日:2016-01-12

    申请号:US13908160

    申请日:2013-06-03

    申请人: Xilinx, Inc.

    IPC分类号: G06F12/00

    摘要: A circuit for enabling a modification of an input data stream is described. The circuit comprises a first plurality of registers coupled in series; an input register of the first plurality of registers coupled to receive the input data stream; an output register of the first plurality of registers positioned at an end of the first plurality of registers; and a control circuit enabling a data value which is independent of the input data stream to be generated as an output of the circuit at a predetermined time.

    摘要翻译: 描述了能够修改输入数据流的电路。 电路包括串联耦合的第一多个寄存器; 耦合以接收所述输入数据流的所述第一多个寄存器的输入寄存器; 所述第一多个寄存器的输出寄存器位于所述第一多个寄存器的一端; 以及控制电路,使得能够在预定时间内产生独立于输入数据流的数据值作为电路的输出。

    Synthesis flow for formal verification
    13.
    发明授权
    Synthesis flow for formal verification 有权
    合成流程正式验证

    公开(公告)号:US08769450B1

    公开(公告)日:2014-07-01

    申请号:US13931621

    申请日:2013-06-28

    申请人: Xilinx, Inc.

    IPC分类号: G06F9/45

    CPC分类号: G06F17/504

    摘要: Processing a circuit design includes generating a transformation output from a transformation input for each of a plurality of transformations of a synthesis flow applied to the circuit design. For each transformation, the transformation input and the transformation output represent the circuit design. At least one circuit element is changed from the transformation input to the transformation output. For each transformation, a hardware description language representation of the transformation input and a hardware description language representation of the transformation output are generated. For each transformation, determining whether the hardware description language representation of the transformation input is equivalent to the hardware description language representation of the transformation output.

    摘要翻译: 处理电路设计包括为应用于电路设计的合成流的多个变换中的每一个生成来自变换输入的变换输出。 对于每个变换,变换输入和变换输出表示电路设计。 至少一个电路元件从变换输入改变为变换输出。 对于每个变换,生成变换输入的硬件描述语言表示和变换输出的硬件描述语言表示。 对于每个变换,确定变换输入的硬件描述语言表示是否等同于转换输出的硬件描述语言表示。

    Multiple output constrained input lookup table generation

    公开(公告)号:US10943043B1

    公开(公告)日:2021-03-09

    申请号:US16831229

    申请日:2020-03-26

    申请人: XILINX, INC.

    摘要: Examples described herein provide a method for optimizing a netlist for an integrated circuit device. The method generally includes receiving a netlist comprising a first lookup table, and upstream logic, wherein the upstream logic receives a plurality of input signals and comprises at least one output connected as at least one input to the first lookup table, wherein the first lookup table comprises an unused input and multiple outputs; mapping the plurality of input signals directly to the at least one input and the unused input of the first lookup table; validating the mapping by monitoring the multiple outputs of the first lookup table; and upon a successful validation, optimizing the netlist by removing the upstream logic and reconnecting the plurality of input signals to the at least one input and the unused input of the first lookup table.