公开(公告)号：US10366001B1

公开(公告)日：2019-07-30

申请号：US15706255

申请日：2017-09-15

申请人： Xilinx, Inc.

发明人： Nithin Kumar Guggilla ,  Chaithanya Dudha ,  Krishna Garlapati ,  Chun Zhang ,  Fan Zhang ,  Anup Kumar Sultania

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F1/3287 ,  G06F13/00 ,  G06F13/28

摘要： Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.

公开(公告)号：US10943043B1

公开(公告)日：2021-03-09

申请号：US16831229

申请日：2020-03-26

申请人： XILINX, INC.

发明人： Jichun Wang ,  Chun Zhang ,  Fan Zhang ,  Bing Tian

IPC分类号： G06F30/30 ,  G06F30/34 ,  G06F30/327 ,  G06F30/337 ,  G06F30/343 ,  G06F30/323

摘要： Examples described herein provide a method for optimizing a netlist for an integrated circuit device. The method generally includes receiving a netlist comprising a first lookup table, and upstream logic, wherein the upstream logic receives a plurality of input signals and comprises at least one output connected as at least one input to the first lookup table, wherein the first lookup table comprises an unused input and multiple outputs; mapping the plurality of input signals directly to the at least one input and the unused input of the first lookup table; validating the mapping by monitoring the multiple outputs of the first lookup table; and upon a successful validation, optimizing the netlist by removing the upstream logic and reconnecting the plurality of input signals to the at least one input and the unused input of the first lookup table.

公开(公告)号：US20240193225A1

公开(公告)日：2024-06-13

申请号：US18065491

申请日：2022-12-13

申请人： Xilinx, Inc.

发明人： Srijan Tiwary ,  Fan Zhang ,  Sumanta Datta ,  Aman Gayasen

IPC分类号： G06F17/16 ,  G06F7/487 ,  G06F7/72

CPC分类号： G06F17/16 ,  G06F7/4876 ,  G06F7/727

摘要： Parameters defining a matrix multiply operation to be implemented in a data processing array can be received. A formulation of the matrix multiply operation is generated based on the parameters. A matrix multiply solution is determined for performing the matrix multiply operation in the data processing array. The matrix multiply solution specifies a spatial and temporal partitioning of the matrix multiply operation for implementation in the data processing array. Synthesizable program code is generated that defines an interface for the data processing array based on the matrix multiply solution. The interface is configured to partition and transfer input data to the data processing array from an external memory and convey output data from the data processing array to the external memory.

公开(公告)号：US10302698B1

公开(公告)日：2019-05-28

申请号：US15589648

申请日：2017-05-08

申请人： Xilinx, Inc.

发明人： Fan Zhang ,  Anup K. Sultania

IPC分类号： G01R31/00 ,  G01R31/3177 ,  G01R31/317

摘要： Disclosed approaches of determining an estimated glitch toggle rate at an output of a logic circuit include inputting functional static probabilities of combinations of states of the plurality of inputs and a generated glitch toggle rate of the logic circuit. Each functional static probability indicates a probability of the states of the inputs of the combination. For each input of the plurality of inputs to the logic circuit, a Boolean Difference Function (BDF) of the input is generated. A maximum glitch rate, which is the estimated glitch toggle rate, is determined based on the generated glitch toggle rate and the functional static probabilities associated with selected combinations of states of the BDF.

公开(公告)号：US09881112B1

公开(公告)日：2018-01-30

申请号：US14677868

申请日：2015-04-02

申请人： Xilinx, Inc.

发明人： Fan Zhang ,  Anup K. Sultania ,  Guenter Stenz

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Vectorless dynamic power estimation for a circuit design may include forming, using a processor, a complex basic element within the circuit design, determining, using the processor, initial toggle rates for basic elements within the circuit design, and determining, using the processor, an initial toggle rate for the complex basic element. Vectorless dynamic power estimation further may include generating, using the processor, final toggle rates by updating the initial toggle rates according to a control signal analysis and calculating, using the processor, dynamic power dissipation for the circuit design using the final toggle rates.