Invention Grant
- Patent Title: Multiple output constrained input lookup table generation
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Application No.: US16831229Application Date: 2020-03-26
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Publication No.: US10943043B1Publication Date: 2021-03-09
- Inventor: Jichun Wang , Chun Zhang , Fan Zhang , Bing Tian
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F30/30
- IPC: G06F30/30 ; G06F30/34 ; G06F30/327 ; G06F30/337 ; G06F30/343 ; G06F30/323

Abstract:
Examples described herein provide a method for optimizing a netlist for an integrated circuit device. The method generally includes receiving a netlist comprising a first lookup table, and upstream logic, wherein the upstream logic receives a plurality of input signals and comprises at least one output connected as at least one input to the first lookup table, wherein the first lookup table comprises an unused input and multiple outputs; mapping the plurality of input signals directly to the at least one input and the unused input of the first lookup table; validating the mapping by monitoring the multiple outputs of the first lookup table; and upon a successful validation, optimizing the netlist by removing the upstream logic and reconnecting the plurality of input signals to the at least one input and the unused input of the first lookup table.
Information query