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    Single port memory with multiple memory operations per clock cycle
    12.
    发明授权
    Single port memory with multiple memory operations per clock cycle 有权

    公开(公告)号：US12190994B2

    公开(公告)日：2025-01-07

    申请号：US18090574

    申请日：2022-12-29

    Applicant: XILINX, INC.

    Inventor： Kumar Rahul ,  Santosh Yachareni ,  Mahendrakumar Gunasekaran ,  Mohammad Anees

    IPC: G11C7/22 ,  G11C7/10

    Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

    Single event upset tolerant memory device
    13.
    发明授权
    Single event upset tolerant memory device 有权

    公开(公告)号：US12045469B2

    公开(公告)日：2024-07-23

    申请号：US18082223

    申请日：2022-12-15

    Applicant: XILINX, INC.

    Inventor： Kumar Rahul ,  John J. Wuu ,  Santosh Yachareni ,  Nui Chong ,  Cheang Whang Chang

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

    Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

    Multi-chip stacked devices
    14.
    发明授权
    Multi-chip stacked devices 有权

    公开(公告)号：US11127718B2

    公开(公告)日：2021-09-21

    申请号：US16741319

    申请日：2020-01-13

    Applicant: XILINX, INC.

    Inventor： Anil Kumar Kandala ,  Vijay Kumar Koganti ,  Santosh Yachareni

    IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

    Abstract: Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.

    Low offset and enhanced write margin for stacked fabric dies
    15.
    发明授权
    Low offset and enhanced write margin for stacked fabric dies 有权

    公开(公告)号：US11043263B1

    公开(公告)日：2021-06-22

    申请号：US16683846

    申请日：2019-11-14

    Applicant: Xilinx, Inc.

    Inventor： Sree R K C Saraswatula ,  Abhimanyu Kumar ,  Santosh Yachareni ,  Shidong Zhou

    IPC: G11C7/00 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412

    Abstract: A device includes an amplifier, a plurality of selector circuitries, and a plurality of fabric dies. The amplifier is configured to output a supply power signal. Each selector circuitry of the plurality of selector circuitries receives the supply power signal from the amplifier. Each fabric die of the plurality of fabric dies has a corresponding selector circuitry of the plurality of selector circuitries. Each selector circuitry corresponding to a die of the plurality of dies is configured to provide the supply power signal received from the amplifier to its corresponding die responsive to a selection signal being asserted. Selector circuitries of the plurality of selector circuitries corresponding to unselected dies of the plurality of dies pull address supply power for the unselected dies to an input other than the supply power signal of the selector circuitries corresponding to the unselected die.

    Multi-chip devices
    19.
    发明授权
    Multi-chip devices 有权

    公开(公告)号：US11423952B2

    公开(公告)日：2022-08-23

    申请号：US16715249

    申请日：2019-12-16

    Applicant: XILINX, INC.

    Inventor： Narendra Kumar Pulipati ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou

    IPC: G11C5/14 ,  H01L25/18 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094

    Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

    MULTI-CHIP DEVICES
    20.
    发明申请
    MULTI-CHIP DEVICES 有权

    公开(公告)号：US20210183412A1

    公开(公告)日：2021-06-17

    申请号：US16715249

    申请日：2019-12-16

    Applicant: XILINX, INC.

    Inventor： Narendra Kumar Pulipati ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou

    IPC: G11C5/14 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0185 ,  H01L25/18

    Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

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