公开(公告)号：US10466275B1

公开(公告)日：2019-11-05

申请号：US16022403

申请日：2018-06-28

Applicant: Xilinx, Inc.

Inventor： Sandeep Vundavalli ,  Sree RKC Saraswatula ,  James D. Wesselkamper ,  Santosh Yachareni ,  Shidong Zhou ,  Anil Kumar Kandala

IPC: G11C29/00 ,  G01R11/24 ,  G01R31/30 ,  G06F21/86 ,  G06F21/76 ,  G01R22/06

Abstract: Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

公开(公告)号：US11423952B2

公开(公告)日：2022-08-23

申请号：US16715249

申请日：2019-12-16

Applicant: XILINX, INC.

Inventor： Narendra Kumar Pulipati ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou

IPC: G11C5/14 ,  H01L25/18 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094

Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

公开(公告)号：US20210183412A1

公开(公告)日：2021-06-17

申请号：US16715249

申请日：2019-12-16

Applicant: XILINX, INC.

Inventor： Narendra Kumar Pulipati ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou

IPC: G11C5/14 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0185 ,  H01L25/18

Abstract: Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

公开(公告)号：US10411710B1

公开(公告)日：2019-09-10

申请号：US16211149

申请日：2018-12-05

Applicant: Xilinx, Inc.

Inventor： Shidong Zhou ,  Sree RKC Saraswatula ,  Jing Jing Chen ,  Teja Masina ,  Narendra Kumar Pulipati ,  Santosh Yachareni

IPC: H03K19/177

Abstract: An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

公开(公告)号：US10396799B1

公开(公告)日：2019-08-27

申请号：US15839462

申请日：2017-12-12

Applicant: Xilinx, Inc.

Inventor： Vishwak R Manda ,  Sree RKC Saraswatula ,  Santosh Yachareni ,  Shidong Zhou ,  Jing Jing Chen ,  Michael Tsivyan

IPC: H03K19/177 ,  H03K19/00 ,  H03K19/0185

Abstract: A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.