公开(公告)号：US4821225A

公开(公告)日：1989-04-11

申请号：US042532

申请日：1987-04-27

Applicant: Hideki Ando ,  Hirohisa Machida

Inventor： Hideki Ando ,  Hirohisa Machida

IPC: G06F7/00 ,  G06F7/575 ,  G06F7/38

CPC classification number: G06F7/575

Abstract: The present invention is an arithmetic and logic unit of a microprocessor having hardware improved to execute specified operation such as operation of MAD (modified addition) by a small number of instruction steps.The arithmetic and logic unit of the present invention has a control portion provided with a control circuit for performing the specified operation such as operation of MAD by a small number of instruction steps.

Abstract translation: 本发明是具有改进的硬件的微处理器的算术和逻辑单元，以通过少量指令步骤执行诸如MAD（修改加法）的操作的指定操作。 本发明的算术和逻辑单元具有控制部分，该控制部分设置有用于通过少量指令步骤执行诸如MAD的操作的指定操作的控制电路。

公开(公告)号：US06637003B1

公开(公告)日：2003-10-21

申请号：US09704797

申请日：2000-11-03

Applicant: Michiru Hori ,  Hirohisa Machida

Inventor： Michiru Hori ,  Hirohisa Machida

IPC: H03M1303

CPC classification number: H03M13/41

Abstract: A viterbi decoder includes a viterbi decoding section which decodes input data, and a coding unit which codes the data decoded by the decoding unit. The number of bit error corrections in the output of the coding unit during a measurement period which is set externally are detected. Further, a synchronized state is detected based on the detected number of bit error corrections and a threshold. A threshold detecting unit detects the threshold from the detected number of bit error corrections during a threshold detection period that includes the measurement period.

Abstract translation: 维特比解码器包括对输入数据进行解码的维特比解码部分和对由解码单元解码的数据进行编码的编码单元。 检测在外部设定的测量周期期间编码单元的输出中的位误差校正次数。 此外，基于检测到的位错误校正数和阈值来检测同步状态。 阈值检测单元在包括测量周期的阈值检测周期期间从检测到的位错误校正数量检测阈值。

公开(公告)号：US5875323A

公开(公告)日：1999-02-23

申请号：US547798

申请日：1995-10-25

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/42 ,  G06F9/302

CPC classification number: G06F9/30167 ,  G06F9/30163

Abstract: To obtain a high performance computer decreased in the number of commands to be executed. A control circuit receives a command (CMD), and outputs a special command signal which becomes "H" when the command (CMD) instructs "push" command, to a register file. The register file, when the special command signal is "H", outputs the stored data value of register as register data regardless of the values of read register address signals, and and outputs the stored data value of register as register data. An ALU adds the register data and control data, and outputs the ALU operation result to the register file. An address adder adds the register data and control data, and outputs the address addition result to an external memory.

Abstract translation: 要获得高性能计算机的命令数量会减少。 控制电路接收命令（CMD），并且当命令（CMD）指示“推”命令时，将其输出为“H”的特殊命令信号给寄存器文件。 当特殊命令信号为“H”时，寄存器文件将存储的寄存器数据值作为寄存器数据输出，而与读取寄存器地址信号的值无关，并将存储的寄存器数据值作为寄存器数据输出。 ALU添加寄存器数据和控制数据，并将ALU运算结果输出到寄存器文件。 地址加法器将寄存器数据和控制数据相加，并将地址相加结果输出到外部存储器。

公开(公告)号：US5468977A

公开(公告)日：1995-11-21

申请号：US242153

申请日：1994-05-13

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: H01L21/82 ,  H01L27/02 ,  H01L27/118 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

CPC classification number: H01L27/0207

Abstract: A semiconductor integrated circuit device designed with CAD is formed of a plurality of standard cells including at least four I/O terminals. Each standard cell includes a metal interconnection for a power supply and a metal interconnection for the ground, and also includes an active element formation region and a metal interconnection layer isolated from respective interconnection layers and coupled to a plurality of I/O terminals at a position above it. If it is desired to use the metal interconnection as a power signal line, a via hole is formed in an insulator film, and the metal interconnection layer and the metal interconnection for the power supply are coupled together therethrough.

Abstract translation: 设计有CAD的半导体集成电路装置由包括至少四个I / O端子的多个标准单元形成。 每个标准单元包括用于电源的金属互连和用于接地的金属互连，并且还包括有源元件形成区域和与相应互连层隔离的金属互连层，并且在一个位置处耦合到多个I / O端子 它上面。 如果希望使用金属互连作为电源信号线，则在绝缘膜中形成通孔，并且金属互连层和用于电源的金属互连通过其耦合在一起。

公开(公告)号：US5233691A

公开(公告)日：1993-08-03

申请号：US450633

申请日：1989-12-13

Applicant: Hideki Ando ,  Hirohisa Machida

Inventor： Hideki Ando ,  Hirohisa Machida

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F9/30127 ,  G06F9/4425

Abstract: A reduced instruction set computer which adopts a configuration of controlling in a manner that in response to an access to a register file, the using state of an external bus or the like, if possible, in a period before an overflow of the register file takes place, register windows used in the procedure called in the past are made to save in advance into a stack of a memory, as a result, there is a high possibility that processing of making the register windows save into the stack of the memory has been already completed even if an overflow takes place in the register file, whereby being capable of dispensing with saving processing of the register window into the stack at this point.

Abstract translation: 一种简化指令集计算机，其以在寄存器文件的溢出之前的一段时间内以可能的方式响应于访问寄存器文件，外部总线的使用状态等的方式进行控制的配置 过去调用的过程中使用的寄存器窗口被预先保存到存储器的堆栈中，结果是存储器的堆栈中的寄存器窗口的处理被存储的可能性很高 即使在寄存器文件中发生溢出也已经完成，从而能够在此时将登记窗口的保存处理分配到堆栈中。

公开(公告)号：US5130692A

公开(公告)日：1992-07-14

申请号：US643987

申请日：1991-01-22

Applicant: Hideaki Ando ,  Hirohisa Machida

Inventor： Hideaki Ando ,  Hirohisa Machida

IPC: G06F7/02 ,  G06F12/10 ,  G06F12/12 ,  G11C15/00

CPC classification number: G11C15/00 ,  G06F12/123 ,  G06F7/02 ,  G06F12/1027

Abstract: An improved data comparison circuit for comparing two pieces of data having 12 bits is disclosed. In the data comparison circuit, cell circuits compare two pieces of data for every corresponding 4 bits. When a match is detected in the comparison of a set of 4 bits, a signal representative of the comparison result of the lower-order bits is bypassed. That is, by bypassing a signal representative of the comparison result of the lower order bits through the cell circuit in which the match is detected, the delay of signal propagation which may occur in the cell circuit in which the match is detected can be prevented.

Abstract translation: 公开了一种用于比较具有12位的两个数据的改进的数据比较电路。 在数据比较电路中，单元电路对每个相应的4位数据进行比较。 当在一组4比特的比较中检测到匹配时，旁路表示低位比特的比较结果的信号。 也就是说，通过旁路表示通过检测到匹配的单元电路的低阶位的比较结果的信号，可以防止在其中检测到匹配的单元电路中可能发生的信号传播的延迟。

公开(公告)号：US5812845A

公开(公告)日：1998-09-22

申请号：US719545

申请日：1996-09-25

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30032 ,  G06F9/3824 ,  G06F9/3885

Abstract: A computer of a pipeline type is provided in which a processing of exchanging data stored in two data storing portions can be performed at a high speed by adding a comparatively simple circuit structure without increasing the operation processing time of an instruction executing portion. An exclusive-OR gate executes the exclusive-OR of the ordinary operation result (ALU operation result) on the E-stage stored in an operation result register and data stored in a bus register, and outputs the EXOR operation result to a selector. The selector outputs one of the EXOR operation result and the ALU operation result stored in the operation result register based on SWAP indication information stored in a register for SWAP instructions.

Abstract translation: 提供了一种管道类型的计算机，其中通过添加相对简单的电路结构，可以高速地执行存储在两个数据存储部分中的数据交换处理，而不增加指令执行部分的操作处理时间。 异或门对运算结果寄存器中存储的E级和存储在总线寄存器中的数据执行普通运算结果（ALU运算结果）的异或运算，并将EXOR运算结果输出到选择器。 选择器基于存储在用于SWAP指令的寄存器中的SWAP指示信息输出存储在操作结果寄存器中的EXOR运算结果和ALU运算结果之一。

公开(公告)号：US5805490A

公开(公告)日：1998-09-08

申请号：US500324

申请日：1995-07-10

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F12/00 ,  G06F12/10 ,  G11C15/00 ,  G11C15/04 ,  G06F7/50

CPC classification number: G06F12/1027

Abstract: A TLB circuit includes a memory circuit and a FAC-CAM circuit, a kind of associative memory. The FAC-CAM circuit receives two data entries, and computes a virtual address while comparing the virtual address with prescribed values stored therein. As the result of the comparison, when the prescribed value which is coincident with the virtual address is found, at least one of a group of coincidence signals is activated and a hit signal is outputted. Thus, the associative memory utilizing the FAC circuit enables a high-speed addition operation and comparison.

Abstract translation: TLB电路包括存储器电路和FAC-CAM电路，一种关联存储器。 FAC-CAM电路接收两个数据条目，并且在将虚拟地址与其中存储的规定值进行比较时计算虚拟地址。 作为比较的结果，当找到与虚拟地址一致的规定值时，启动一组重合信号中的至少一个并输出命中信号。 因此，利用FAC电路的关联存储器能够实现高速的相加操作和比较。

公开(公告)号：US5603023A

公开(公告)日：1997-02-11

申请号：US557503

申请日：1995-11-14

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F7/24 ,  G06F17/30

CPC classification number: G06F7/24 ,  G06F2207/222 ,  Y10S707/99937

Abstract: A heapsort processor includes a first decoder for selecting a parent macro cell and a second decoder for selecting macro cell pair 480 having twice or twice plus one the address of the parent. The data of the parent is read to the first bit line, while data of a macro cell storing larger data in macro cell pair is read to the second bit line. The processor further includes a circuit for exchanging, when the data on the second bit line is larger than the data on the first bit line, the data of these bit lines and for writing the exchanged data to original macro cells. This enables generation of heap data. When a macro cell storing a root is selected by disabling the second decoder, part of a heapsort algorithm can be implemented in a hardware.

Abstract translation: 堆叠处理器包括用于选择母宏小区的第一解码器和用于选择具有两倍或两倍加上父母地址的宏小区对480的第二解码器。 父数据被读取到第一位线，而在宏单元对中存储较大数据的宏单元的数据被读取到第二位线。 处理器还包括一个电路，当第二位线上的数据大于第一位线上的数据时，这些位线的数据和用于将交换的数据写入原始宏单元的数据。 这样可以生成堆数据。 当通过禁用第二解码器来选择存储根的宏小区时，可以在硬件中实现部分堆积算法。

公开(公告)号：US5511189A

公开(公告)日：1996-04-23

申请号：US310745

申请日：1994-09-22

Applicant: Hirohisa Machida

Inventor： Hirohisa Machida

IPC: G06F7/24

CPC classification number: G06F7/24

Abstract: Disclosed is a sorting apparatus for sorting applied n data. Data to be sorted are once held within data registers. Odd-numbered comparison/exchange circuits and even-numbered comparison/exchange circuits are alternately enabled, so that two data held between adjacent two data registers are compared/exchanged. Comparison/exchange circuits apply signals indicating data exchange to a sorting completion detecting circuit. Since sorting completion detecting circuit detects completion of sorting in response to the applied exchange signal, an operation after the completion of sorting is stopped. That is, a processing in the sorting apparatus ends in a short time.

Abstract translation: 公开了一种用于对应用的n个数据进行排序的分类装置。 要排序的数据一旦保存在数据寄存器中。 交替使能奇数比较/交换电路和偶数比较/交换电路，使得相邻两个数据寄存器之间保存的两个数据进行比较/交换。 比较/交换电路将指示数据交换的信号应用于排序完成检测电路。 由于排序完成检测电路响应于所应用的交换信号来检测排序的完成，因此停止排序完成之后的操作。 也就是说，分拣装置中的处理在短时间内结束。