公开(公告)号：US11422475B2

公开(公告)日：2022-08-23

申请号：US16722621

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/20 ,  H01L21/768 ,  G03F7/004 ,  G03F7/00 ,  G03F7/09

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US11183422B2

公开(公告)日：2021-11-23

申请号：US17065253

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/528

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion.

公开(公告)号：US10818596B2

公开(公告)日：2020-10-27

申请号：US16124567

申请日：2018-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Tien-I Bao ,  Tien-Lu Lin ,  Wei-Chen Chu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphene layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

公开(公告)号：US20190244902A1

公开(公告)日：2019-08-08

申请号：US16384673

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Wei-Chen Chu

IPC: H01L23/535 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/535 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

公开(公告)号：US10020261B2

公开(公告)日：2018-07-10

申请号：US15294286

申请日：2016-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Wei-Chen Chu

IPC: H01L23/48 ,  H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

公开(公告)号：US20240085803A1

公开(公告)日：2024-03-14

申请号：US18514254

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/00 ,  G03F7/004 ,  G03F7/09 ,  H01L21/768

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

公开(公告)号：US10522469B2

公开(公告)日：2019-12-31

申请号：US16384673

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Tien Wu ,  Hsiang-Wei Liu ,  Wei-Chen Chu

IPC: H01L23/48 ,  H01L23/535 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/033

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

公开(公告)号：US10074607B2

公开(公告)日：2018-09-11

申请号：US15016866

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Tien-I Bao ,  Tien-Lu Lin ,  Wei-Chen Chu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53276

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.

公开(公告)号：US20180138076A1

公开(公告)日：2018-05-17

申请号：US15353850

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsin-Ping Chen ,  Chih-Wei Lu ,  Chung-Ju Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5283

Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.

公开(公告)号：US11860550B2

公开(公告)日：2024-01-02

申请号：US17868398

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Wei-Chen Chu ,  Hsiang-Wei Liu ,  Shau-Lin Shue ,  Li-Lin Su ,  Yung-Hsu Wu

IPC: G03F7/00 ,  H01L21/768 ,  G03F7/004 ,  G03F7/09

CPC classification number: G03F7/70633 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0047 ,  G03F7/094 ,  G03F7/70625 ,  H01L21/7682 ,  H01L21/76807 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/76849

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.