公开(公告)号：US20180190652A1

公开(公告)日：2018-07-05

申请号：US15491206

申请日：2017-04-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Chih-Liang CHEN ,  Shi Ning JU

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545

Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

公开(公告)号：US20250142954A1

公开(公告)日：2025-05-01

申请号：US19007076

申请日：2024-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H10D84/85 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H10D30/01 ,  H10D30/62 ,  H10D30/69 ,  H10D62/10 ,  H10D62/13 ,  H10D62/822 ,  H10D62/832 ,  H10D62/834 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes a semiconductor channel region, a source/drain region, and a contact structure. The semiconductor channel region is over a substrate. The source/drain region is adjacent the semiconductor channel region. The source/drain region has a notched corner. The contact structure has a portion inlaid in the notched corner in the source/drain region.

公开(公告)号：US20220352164A1

公开(公告)日：2022-11-03

申请号：US17861565

申请日：2022-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.

公开(公告)号：US20220140103A1

公开(公告)日：2022-05-05

申请号：US17576854

申请日：2022-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kai-Chieh YANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.

公开(公告)号：US20210265485A1

公开(公告)日：2021-08-26

申请号：US17314763

申请日：2021-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first dielectric fin, a semiconductor fin, a metal gate structure, an epitaxy structure, and a contact etch stop layer. The first dielectric fin is disposed over the substrate. The semiconductor fin is disposed over the substrate, in which along a lengthwise direction of the first dielectric fin and the semiconductor fin, the first dielectric fin is in contact with a first sidewall of the semiconductor fin. The metal gate structure crosses the first dielectric fin and the semiconductor fin. The epitaxy structure is over and in contact with the semiconductor fin. The contact etch stop layer is over and in contact with first dielectric fin.

公开(公告)号：US20200259014A1

公开(公告)日：2020-08-13

申请号：US16859779

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/16 ,  H01L27/088

Abstract: A method includes forming a first semiconductor layer over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are etched to form a fin structure that extends from the substrate. The fin structure has a remaining portion of first semiconductor layer and a remaining portion of the second semiconductor layer atop the remaining portion of the first semiconductor layer. A capping layer is formed to wrap around three sides of the fin structure. At least a portion of the capping layer and at least a portion of the remaining portion of the second semiconductor layer in the fin structure are oxidized to form an oxide layer wrapping around three sides of the fin structure.

公开(公告)号：US20200052084A1

公开(公告)日：2020-02-13

申请号：US16655079

申请日：2019-10-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US20190164772A1

公开(公告)日：2019-05-30

申请号：US15967100

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Yuan TSENG ,  Yu-Tien SHEN ,  Wei-Liang LIN ,  Chih-Ming LAI ,  Kuo-Cheng CHING ,  Shi Ning JU ,  Li-Te LIN ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/32

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

公开(公告)号：US20190139777A1

公开(公告)日：2019-05-09

申请号：US16221766

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hao CHANG ,  Chao-Hsien HUANG ,  Wen-Ting LAN ,  Shi-Ning JU ,  Li-Te LIN ,  Kuo-Cheng CHING

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method includes forming a mandrel structure over a semiconductor substrate. A first spacer and a second spacer are formed alongside the mandrel structure. A mask layer is over a first portion of the first spacer, in which a second portion of the first spacer and the second spacer are exposed from the mask layer. The exposed second spacer is etched, in which etching the exposed second spacer is performed such that a polymer is formed over a top surface of the exposed second portion of the first spacer. The mask layer, the polymer, and the mandrel structure are removed. The semiconductor substrate is patterned using the first spacer.

公开(公告)号：US20190115438A1

公开(公告)日：2019-04-18

申请号：US16206730

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/04 ,  H01L29/78 ,  H01L29/66

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.