公开(公告)号：US20200381043A1

公开(公告)日：2020-12-03

申请号：US16997857

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

IPC: G11C11/419

Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide a first power voltage via a conductive line for the plurality of first memory cells, and to provide a second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells via the conductive line and for corresponding memory cells of the plurality of second memory cells. A circuit structure of the power circuit is different from a circuit structure of the header circuit.

公开(公告)号：US20200293417A1

公开(公告)日：2020-09-17

申请号：US16888013

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung CHANG ,  Atul KATOCH ,  Chia-En HUANG ,  Ching-Wei WU ,  Donald G. MIKAN, JR. ,  Hao-I YANG ,  Kao-Cheng LIN ,  Ming-Chien TSAI ,  Saman M.I. ADHAM ,  Tsung-Yung CHANG ,  Uppu Sharath CHANDRA

IPC: G06F11/263 ,  G06F1/10 ,  G06F11/22 ,  G06F11/267 ,  G11C29/48 ,  G11C29/32 ,  G11C29/12

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US20190004915A1

公开(公告)日：2019-01-03

申请号：US15700877

申请日：2017-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hung CHANG ,  Atul KATOCH ,  Chia-En HUANG ,  Ching-Wei WU ,  Donald G. MIKAN, JR. ,  Hao-I YANG ,  Kao-Cheng LIN ,  Ming-Chien TSAI ,  Saman M.I ADHAM ,  Tsung-Yung CHANG ,  Uppu Sharath CHANDRA

IPC: G06F11/263 ,  G06F11/22 ,  G06F1/10

Abstract: An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

公开(公告)号：US20150063040A1

公开(公告)日：2015-03-05

申请号：US14014431

申请日：2013-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Min CHAN ,  Kao-Cheng LIN ,  Yen-Huei CHEN

IPC: G11C11/419

CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C5/063 ,  G11C8/08 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: A semiconductor memory comprises a dual-port memory array having a plurality of cross-access dual-port bit cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of cross-access dual-port bit cells has two cross-access ports for read and write of one or more bits of data to the cross-access dual port bit cell. The semiconductor memory further comprises a pair of word lines associated with at least one of the plurality of rows of the dual-port memory array, wherein the pair of word lines is configured to carry a pair of row selection signals for enabling one or more read and write operations on one or more cross-access dual-port bit cells in the row. The semiconductor memory further comprises a pair of column selection lines associated with at least one of the plurality of columns of the dual port memory array, wherein the pair of column selection lines is configured to carry a pair of column selection signals for enabling the cross-access dual-port bit cells in the column during the read and write operations.

Abstract translation: 半导体存储器包括双端口存储器阵列，其具有以多行和多列布置的多个交叉访问双端口位单元，其中多个交叉访问双端口位单元中的每一个具有两个 交叉访问端口用于读取和写入一个或多个位数据到交叉访问双端口位单元。 半导体存储器还包括与双端口存储器阵列的多行中的至少一个相关联的一对字线，其中该对字线被配置为携带一对行选择信号，以使一个或多个读取 并对行中的一个或多个交叉访问双端口位单元进行写入操作。 半导体存储器还包括与双端口存储器阵列的多个列中的至少一个相关联的一对列选择线，其中该列选择线被配置为承载一对列选择信号， 在读取和写入操作期间访问列中的双端口位单元。