公开(公告)号：US20200319565A1

公开(公告)日：2020-10-08

申请号：US16905167

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Joy Cheng

IPC: G03F7/20 ,  G03F7/038 ,  G03F7/039 ,  G03F7/06 ,  G03F7/16 ,  G03F7/30 ,  G03F7/32 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027

Abstract: A layer is formed over a wafer. The layer contains a material that is sensitive to an extreme ultraviolet (EUV) radiation. A first baking process is performed to the layer. The first baking process is performed with a first humidity level that is greater than about 44%. After the first baking process, the layer is exposed to EUV radiation. A second baking process is performed to the layer. The second baking process is performed with a second humidity level that is greater than about 44%. The layer is rinsed with a liquid that contains water before the second baking process or after the second baking process. After the exposing, the layer is developed with a developer solution that contains water.

公开(公告)号：US10790155B2

公开(公告)日：2020-09-29

申请号：US16240402

申请日：2019-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Yung-Sung Yen ,  Ken-Hsien Hsieh ,  Chin-Hsiang Lin

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

公开(公告)号：US20200279743A1

公开(公告)日：2020-09-03

申请号：US16877755

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tien Shen ,  Chi-Cheng Hung ,  Chin-Hsiang Lin ,  Chien-Wei Wang ,  Ching-Yu Chang ,  Chih-Yuan Ting ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yuan-Hsiang Lung ,  Yen-Ming Chen ,  Yung-Sung Yen

IPC: H01L21/265 ,  H01L21/311 ,  H01L21/033

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

公开(公告)号：US10741391B2

公开(公告)日：2020-08-11

申请号：US16021521

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang

IPC: H01L21/027 ,  G03F7/20 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary, and the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. The method also includes exposing a portion of the resist layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process. The method further includes etching a portion of the resist layer to form a patterned resist layer and patterning the material layer by using the patterned resist layer as a mask. The method also includes removing the patterned resist layer.

公开(公告)号：US10691023B2

公开(公告)日：2020-06-23

申请号：US15940107

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/40 ,  H01L21/027 ,  G03F7/30 ,  G03F7/20

Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.

公开(公告)号：US10672619B2

公开(公告)日：2020-06-02

申请号：US15628355

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/308 ,  G03F7/40 ,  G03F7/26

Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.

公开(公告)号：US20200152468A1

公开(公告)日：2020-05-14

申请号：US16725120

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei Wang ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/288 ,  H01L21/3213

Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.

公开(公告)号：US20200019070A1

公开(公告)日：2020-01-16

申请号：US16035354

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/20

Abstract: Semiconductor systems, apparatuses and methods are provided. In one embodiment, an extreme ultraviolet lithography system includes a substrate stage configured to secure a substrate at a first vertical level, wherein the substrate is deposited with a resist layer thereon; at least one electrode positioned at a second vertical level above the first vertical level; and a power source configured to apply an electric field across the at least one electrode and the substrate stage, including across a thickness of the resist layer when the substrate is secured on the substrate stage.

公开(公告)号：US10520822B2

公开(公告)日：2019-12-31

申请号：US15639033

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui Weng ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/40 ,  G03F7/039

Abstract: The present disclosure provides lithography resist materials and corresponding lithography techniques for improving lithography resolution, in particular, by reducing swelling of resist layers during development. An exemplary lithography method includes performing a treatment process on a resist layer to cause cross-linking of acid labile group components of the resist layer via cross-linkable functional components, performing an exposure process on the resist layer, and performing a development process on the resist layer. In some implementations, the resist layer includes an exposed portion and an unexposed portion after the exposure process, and the treatment process reduces solubility of the unexposed portion to a developer used during the development process by increasing a molecular weight of a polymer in the unexposed portion. The treatment process is performed before or after the exposure process. The treatment process can include performing a thermal treatment and/or an electromagnetic wave treatment to heat the resist layer.

公开(公告)号：US10515847B2

公开(公告)日：2019-12-24

申请号：US16007648

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang Lin ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L21/027

Abstract: A method for forming openings in an underlayer includes: forming a photoresist layer on an underlayer formed on a substrate; exposing the photoresist layer; forming photoresist patterns by developing the exposed photoresist layer, the photoresist patterns covering regions of the underlayer in which the openings are to be formed; forming a liquid layer over the photoresist patterns; after forming the liquid layer, performing a baking process so as to convert the liquid layer to an organic layer in a solid form; performing an etching back process to remove a portion of the organic layer on a level above the photoresist patterns; removing the photoresist patterns, so as to expose portions of the underlayer by the remaining portion of the organic layer; forming the openings in the underlayer by using the remaining portion of the organic layer as an etching mask; and removing the remaining portion of the organic layer.