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    CLOCK AND DATA RECOVERY CIRCUIT
    12.
    发明申请
    CLOCK AND DATA RECOVERY CIRCUIT 有权

    公开(公告)号：US20210273674A1

    公开(公告)日：2021-09-02

    申请号：US17320568

    申请日：2021-05-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hsiang LAN ,  Cheng-Hsiang HSIEH

    IPC: H04B1/7085 ,  H04L7/00

    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

    HYBRID PHASE LOCK LOOP
    13.
    发明申请
    HYBRID PHASE LOCK LOOP 审中-公开

    公开(公告)号：US20190158102A1

    公开(公告)日：2019-05-23

    申请号：US16189482

    申请日：2018-11-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien TSAI ,  Chih-Hsien CHANG ,  Ruey-Bin SHEEN ,  Cheng-Hsiang HSIEH

    IPC: H03L7/099 ,  H03L7/113 ,  H03L7/183 ,  H03L7/085 ,  H03L7/087

    CPC classification number: H03L7/0991 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/183 ,  H03L2207/06

    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

    MEMS HUMIDITY SENSOR AND METHOD OF MANUFACTURING THE SAME
    14.
    发明申请
    MEMS HUMIDITY SENSOR AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20170248536A1

    公开(公告)日：2017-08-31

    申请号：US15053906

    申请日：2016-02-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Tung-Tsun CHEN ,  Chia-Hua CHU ,  Jui-Cheng HUANG ,  Chun-Wen CHENG ,  Cheng-Hsiang HSIEH

    IPC: G01N27/22

    CPC classification number: G01N27/223 ,  G01N27/226

    Abstract: A micro-electro mechanical system (MEMS) humidity sensor includes a first substrate, a second substrate and a sensing structure. The second substrate is substantially parallel to the first substrate. The sensing structure is between the first substrate and the second substrate, and bonded to a portion of the first substrate and a portion of the second substrate, in which the second substrate includes a conductive layer facing the sensing structure, and a first space between the first substrate and the sensing structure is communicated with or isolated from outside, and a second space between the conductive layer and the sensing structure is communicated with an atmosphere, and the sensing structure, the second space and the conductive layer constitute a capacitor configured to measure permittivity of the atmosphere, and humidity of the atmosphere is derived from the permittivity of the atmosphere, pressure of the atmosphere and temperature.

    CLOCK AND DATA RECOVERY CIRCUIT
    15.
    发明申请
    CLOCK AND DATA RECOVERY CIRCUIT 审中-公开

    公开(公告)号：US20200153478A1

    公开(公告)日：2020-05-14

    申请号：US16742423

    申请日：2020-01-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Hsiang LAN ,  Cheng-Hsiang HSIEH

    IPC: H04B1/7085 ,  H04L7/00

    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

    PHASE LOCKED LOOP
    16.
    发明申请
    PHASE LOCKED LOOP 审中-公开

    公开(公告)号：US20200127668A1

    公开(公告)日：2020-04-23

    申请号：US16723205

    申请日：2019-12-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ting-Kuei KUAN ,  Cheng-Hsiang HSIEH ,  Chen-Ting KO ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG

    IPC: H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/091 ,  H03K7/08 ,  H03L7/097 ,  H03L7/087

    Abstract: Phase-locked loops (PLLs) are provided. A PLL includes a voltage-controlled oscillator (VCO), a frequency divider, a track-and-hold charge pump, and a frequency tracking circuit. The VCO is configured to provide an output clock corresponding to a pumping current. The frequency divider is configured to divide the output clock to provide a feedback signal. The track-and-hold charge pump is configured to provide the pumping current according to a reference clock and the feedback signal. The frequency tracking circuit is configured to decrease frequency error between the feedback signal and the reference clock. The track-and-hold charge pump includes a pumping switch and a pulse width modulator (PWM). The PWM is configured to provide a PWM signal to control the pumping switch according to the reference clock, so as to provide the pumping current corresponding to the feedback signal.

    CLOCK AND DATA RECOVERY CIRCUIT
    17.
    发明申请
    CLOCK AND DATA RECOVERY CIRCUIT 审中-公开

    公开(公告)号：US20190058500A1

    公开(公告)日：2019-02-21

    申请号：US15938264

    申请日：2018-03-28

    Applicant: Taiwan Semiconductor manufacturing Co.,Ltd.

    Inventor： Po-Hsiang LAN ,  Cheng-Hsiang HSIEH

    IPC: H04B1/7085 ,  H04L7/00

    Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a clock and data recovery circuit is disclosed. The circuit includes a third order digital filter, e.g. a finite state machine (FSM) that includes three accumulators connected in series. Among the three accumulators, a first accumulator receives an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle and accumulates input phase codes for different FSM cycles to generate a first order phase code at each FSM cycle; a second accumulator accumulates the input phase codes and first order phase codes for different FSM cycles to generate a second order phase code at each FSM cycle; and a third accumulator accumulates the input phase codes and second order phase codes for different FSM cycles to generate a third order phase code at each FSM cycle.

    Hybrid Phase Lock Loop
    19.
    发明申请
    Hybrid Phase Lock Loop 审中-公开

    公开(公告)号：US20180152192A1

    公开(公告)日：2018-05-31

    申请号：US15428841

    申请日：2017-02-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Hsien TSAI ,  Ruey-Bin SHEEN ,  Chih-Hsien CHANG ,  Cheng-Hsiang HSIEH

    IPC: H03L7/099 ,  H03L7/085

    CPC classification number: H03L7/0991 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/183 ,  H03L2207/06

    Abstract: Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL.

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