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公开(公告)号：US10957672B2
公开(公告)日：2021-03-23
申请号：US15835466
申请日：2017-12-08
发明人： Chi-Yang Yu , Chin-Liang Chen , Chien-Hsun Lee , Kuan-Lin Ho , Yu-Min Liang
IPC分类号： H01L25/065 , H01L23/31 , H01L21/56 , H01L23/538 , H01L23/00 , H01L23/29 , H01L25/00 , H01L21/66
摘要： A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant.
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公开(公告)号：US20220359327A1
公开(公告)日：2022-11-10
申请号：US17870222
申请日：2022-07-21
发明人： Chen-Hua Yu , Chien-Hsun Lee , Jiun Yi Wu
IPC分类号： H01L23/31 , H01L23/498 , H01L21/48 , H01L23/00 , H01L21/56
摘要： An integrated fan out package is utilized in which the dielectric materials of different redistribution layers are utilized to integrate the integrated fan out package process flows with other package applications. In some embodiments an Ajinomoto or prepreg material is utilized as the dielectric in at least some of the overlying redistribution layers.
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公开(公告)号：US20210351076A1
公开(公告)日：2021-11-11
申请号：US17379775
申请日：2021-07-19
发明人： Chen-Hua Yu , Kuo-Chung Yee , Mirng-Ji Lii , Chien-Hsun Lee , Jiun Yi Wu
IPC分类号： H01L21/768 , H01L25/00 , H01L21/56 , H01L23/00 , H01L25/10
摘要： An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.
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公开(公告)号：US11006532B2
公开(公告)日：2021-05-11
申请号：US16860012
申请日：2020-04-27
发明人： Jiun-Yi Wu , Chien-Hsun Lee , Chen-Hua Yu , Chung-Shi Liu
摘要： A circuit carrier and a manufacturing method thereof are provided. The circuit carrier for coupling an electronic device includes a flexible structure and a circuit structure. The flexible structure includes a conductive pattern disposed on a surface of a first dielectric layer. The circuit structure includes a second dielectric layer overlying the surface of the first dielectric layer and a circuit layer disposed on the second dielectric layer and connected to the conductive pattern. The flexible structure is embedded in and electrically connected to the circuit structure, and a portion of the flexible structure extends out from an edge of the circuit structure to be plugged into the electronic device.
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15.发明申请公开(公告)号：US20200275557A1
公开(公告)日：2020-08-27
申请号：US16737912
申请日：2020-01-09
发明人： Jiun-Yi Wu , Chien-Hsun Lee , Chen-Hua Yu , Chung-Shi Liu
IPC分类号： H05K3/40 , H01L23/373 , H05K3/00 , H01L23/538
摘要： A manufacturing method of a circuit board includes the following steps. A conductive plate is provided. The conductive plate is patterned to form ducts. The patterned conductive plate is laminated with a core dielectric layer. The lamination leaves exposed a bottom surface of the patterned conductive plate. Through holes are opened in portions of the core dielectric layer within the ducts. A conductive material is formed in the through holes and over the core dielectric layer to produce a metallization layer electrically insulated from the patterned conductive plate. Dielectric layers and conductive layers are alternately stacked on an upper surface of the core dielectric layer. The conductive layers are electrically connected to the metallization layer.
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公开(公告)号：US20200260595A1
公开(公告)日：2020-08-13
申请号：US16860012
申请日：2020-04-27
发明人： Jiun-Yi Wu , Chien-Hsun Lee , Chen-Hua Yu , Chung-Shi Liu
摘要： A circuit carrier and a manufacturing method thereof are provided. The circuit carrier for coupling an electronic device includes a flexible structure and a circuit structure. The flexible structure includes a conductive pattern disposed on a surface of a first dielectric layer. The circuit structure includes a second dielectric layer overlying the surface of the first dielectric layer and a circuit layer disposed on the second dielectric layer and connected to the conductive pattern, The flexible structure is embedded in and electrically connected to the circuit structure, and a portion of the flexible structure extends out from an edge of the circuit structure to be plugged into the electronic device.
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公开(公告)号：US09807867B2
公开(公告)日：2017-10-31
申请号：US15016147
申请日：2016-02-04
发明人： Jiun-Yi Wu , Chien-Hsun Lee , Chewn-Pu Jou , Fu-Lung Hsueh
IPC分类号： H05K1/02 , H01L21/48 , H01L23/498 , H01L23/552 , H05K3/00 , H05K3/42 , H05K3/40 , H05K1/11
CPC分类号： H05K1/0216 , H01L21/485 , H01L21/486 , H01L23/49827 , H01L23/552 , H05K1/024 , H05K1/0245 , H05K1/113 , H05K1/115 , H05K3/0047 , H05K3/4007 , H05K3/42 , H05K3/423 , H05K2201/0723 , H05K2201/09545 , H05K2201/0959 , H05K2201/09645
摘要： A method for manufacturing an interconnect structure and an interconnect structure are provided. The method includes: forming an opening in a substrate; forming a low-k dielectric block in the opening; forming at least one via in the low-k dielectric block; and forming a conductor in the via. The interconnect structure includes a substrate, a dielectric block, and a conductor. The substrate has an opening therein. The dielectric block is present in the opening of the substrate. The dielectric block has at least one via therein. The dielectric block has a dielectric constant smaller than that of the substrate. The conductor is present in the via of the dielectric block.
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公开(公告)号：US20240047509A1
公开(公告)日：2024-02-08
申请号：US18150624
申请日：2023-01-05
IPC分类号： H01L21/48 , H01L23/498 , H01L23/31 , H01L23/538 , H01L21/56 , H01L25/10 , H01L27/01
CPC分类号： H01L28/10 , H01L21/4857 , H01L23/49816 , H01L23/3128 , H01L23/5381 , H01L23/49822 , H01L23/49833 , H01L21/565 , H01L25/105 , H01L27/01 , H01L23/5386 , H01L21/4853 , H01L23/5385 , H01L23/49838 , H01L21/486 , H01L23/5389 , H10B80/00
摘要： A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.
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公开(公告)号：US20230260862A1
公开(公告)日：2023-08-17
申请号：US18302589
申请日：2023-04-18
发明人： Chien-Hsun Chen , Yu-Ling Tsai , Jiun Yi Wu , Chien-Hsun Lee , Chung-Shi Liu
IPC分类号： H01L23/31 , H01L23/538 , H01L23/498
CPC分类号： H01L23/3121 , H01L23/5384 , H01L23/49827
摘要： In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
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公开(公告)号：US20230253378A1
公开(公告)日：2023-08-10
申请号：US18302165
申请日：2023-04-18
发明人： Chen-Hua Yu , Chien-Hsun Lee , Jiun Yi Wu
IPC分类号： H01L25/10 , H01L23/31 , H01L25/065 , H01L23/00 , H01L23/498 , H01L25/00 , H01L21/56 , H01L21/48 , H01L23/367
CPC分类号： H01L25/105 , H01L23/3121 , H01L25/0655 , H01L24/08 , H01L23/49822 , H01L25/50 , H01L21/561 , H01L21/4857 , H01L23/367 , H01L24/94 , H01L2224/08225 , H01L2225/1058 , H01L2225/1023
摘要： A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.
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