公开(公告)号：US12260116B2

公开(公告)日：2025-03-25

申请号：US18492762

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

IPC: G06F3/06 ,  G06F12/0802

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US12164785B2

公开(公告)日：2024-12-10

申请号：US18196671

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Young Ji ,  Younggeon Yoo ,  Sang-Hwa Jin

IPC: G06F12/00 ,  G06F1/30 ,  G06F3/06

Abstract: The present disclosure provides methods and apparatuses for data loss prevention of a storage device. In some embodiments, the data loss preventing method includes receiving, from a host system, a query plan corresponding to necessary data to be stored in a volatile memory. The data loss preventing method further includes generating, based on the query plan, a data priority list corresponding to the necessary data. The data loss preventing method further includes selecting, based on the data priority list, at least one portion of the volatile memory, when a main power supplied by the host system drops to or below a power level threshold. The data loss preventing method further includes moving the necessary data to the at least one portion of the volatile memory.

公开(公告)号：US11899970B2

公开(公告)日：2024-02-13

申请号：US17742184

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hee Hyun Nam ,  Younggeon Yoo ,  Jeongho Lee ,  Younho Jeon ,  Ipoom Jeong ,  Chanho Yoon

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0611 ,  G06F3/0622 ,  G06F3/0683

Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

公开(公告)号：US11809341B2

公开(公告)日：2023-11-07

申请号：US17378354

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Ipoom Jeong ,  Younggeon Yoo ,  Younho Jeon

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1668 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0673

Abstract: A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.

公开(公告)号：US20230185717A1

公开(公告)日：2023-06-15

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US20210365193A1

公开(公告)日：2021-11-25

申请号：US17181579

申请日：2021-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghyun Hong ,  Youngjin Cho ,  Younggeon Yoo ,  Chanho Yoon ,  Hyeokjun Choe

IPC: G06F3/06 ,  G06F9/48

Abstract: A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

公开(公告)号：US09411679B2

公开(公告)日：2016-08-09

申请号：US13834010

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Junjin Kong ,  Hong Rak Son ,  Younggeon Yoo

IPC: G11C29/00 ,  H03M11/00 ,  G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G11C16/26 ,  G11C11/56 ,  H01L27/115

CPC classification number: G06F11/1008 ,  G06F11/1044 ,  G06F11/1072 ,  G06F12/0246 ,  G11C11/5642 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Disclosed is a bit-state mapping method of a flash memory system which maps m-bit data (m being a natural number more than 2) onto one of 2m states (voltage threshold distributions). The bit-state mapping method includes performing a subset partitioning operation during first to (m−1)th levels under a condition that two adjacent states are processed as one state; and distinguishing between the adjacent states while processing an (m)th level.

Abstract translation: 公开了一种闪存系统的位状态映射方法，其将m比特数据（m是大于2的自然数）映射到2m状态之一（电压阈值分布）。 位状态映射方法包括在将两个相邻状态处理为一个状态的条件下，在第一至第（m-1）级执行子集划分操作; 并且在处理（m）级时区分相邻状态。