-
公开(公告)号：US20170078189A1
公开(公告)日：2017-03-16
申请号：US15132663
申请日：2016-04-19
Inventor： Sungju HAN , Jinho LEE , Kiyoung CHOI , Woong SEO
IPC: H04L12/733 , H04L12/44 , H04L12/741
CPC classification number: H04L45/20 , H04L12/44 , H04L12/5692 , H04L45/121 , H04L45/122 , H04L45/74 , H04L49/109 , H04L49/25
Abstract: Provided is a multi network and method to transmit packets. The multi network includes a mesh network, a tree network, and a network interface connected to the mesh network and the tree network and configured to transmit, through the mesh network and the tree network, a packet generated by a processing unit, of a processing system having plural processing units, at a starting point to a destination point for another processing unit of the processing system and configured to selectively inject the packet into one of the mesh network and the tree network to transmit the packet to the other processing unit.
Abstract translation: 提供了一种传输数据包的多网络和方法。 多网络包括网状网络，树形网络和连接到网状网络和树状网络的网络接口，并且被配置为通过网状网络和树状网络将由处理单元生成的分组发送到处理 系统具有多个处理单元，在处理系统的另一个处理单元的目的地点的起点处，并且被配置为选择性地将分组注入到网状网络和树形网络之一中以将分组发送到另一个处理单元。
-
12.发明申请公开(公告)号：US20160335125A1
公开(公告)日：2016-11-17
申请号：US15146044
申请日：2016-05-04
Inventor： Minseok LEE , John Dongjun KIM , Woong SEO , Soojung RYU , Yeongon CHO
IPC: G06F9/50
CPC classification number: G06F9/5038 , G06F9/46
Abstract: A processor and corresponding method are described including cores having a thread set allocated based on a pre-set implementation order, and a controller configured to receive scheduling information determined based on an implementation pattern regarding the allocated thread set from one of the cores and transmit the scheduling information to another of the cores. The one of cores determines the scheduling information according to characteristics of an application when implementation of the thread set is completed. Each of the cores re-determines an implementation order regarding the allocated thread set based on the determined scheduling information.
Abstract translation: 描述了一种处理器和相应的方法，其包括具有基于预设实现顺序分配的线程集的核心，以及控制器，被配置为接收基于从一个核心分配的线程集合的实现模式确定的调度信息，并发送 将信息调度到另一个核心。 当线程集合的实现完成时，核心之一根据应用的特性确定调度信息。 每个核心基于所确定的调度信息重新确定关于所分配的线程组的实现顺序。
-
公开(公告)号：US20160232093A1
公开(公告)日：2016-08-11
申请号：US15019368
申请日：2016-02-09
Inventor： Namhyung KIM , Junwhan AHN , Kiyoung CHOI , Woong SEO
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0862 , G06F2212/6026 , G06F2212/604
Abstract: A method of managing a cache includes storing first data of an upper level cache in a lower level cache, predicting a reuse distance level of second data having a same signature as the first data based on access information about the first data, and storing the second data in one of the lower level cache and a main memory based on the predicted reuse distance level of the second data.
Abstract translation: 管理高速缓存的方法包括将较高级别高速缓存的第一数据存储在下级高速缓存中，基于关于第一数据的访问信息来预测与第一数据具有相同签名的第二数据的重用距离级别，并存储第二数据 基于第二数据的预测的再利用距离级别，下级缓存和主存储器之一中的数据。
-
公开(公告)号：US20160205042A1
公开(公告)日：2016-07-14
申请号：US14950490
申请日：2015-11-24
Inventor： Woong SEO , Minseok LEE , Dongjun KIM , Soojung RYU , Yeongon CHO
IPC: H04L12/933 , H04L12/761
CPC classification number: H04L49/102 , H04L45/16
Abstract: A method of transceiving data over an on-chip network includes determining whether a packet is received by a first router among a plurality of first routers constituting a ring network; determining a transmission destination of the packet received by the first router; and transmitting the packet to a second router among a plurality of second routers constituting a bus network connected to the first router in response to the determined transmission destination being located on the bus network connected to the first router.
Abstract translation: 一种通过片上网络收发数据的方法包括：确定构成环网的多个第一路由器中的第一路由器是否接收到分组; 确定由第一路由器接收的分组的传输目的地; 以及响应于所确定的发送目的地位于连接到所述第一路由器的总线网络上，将构成连接到所述第一路由器的总线网络的多个第二路由器中的所述分组发送到第二路由器。
-
公开(公告)号：US20160163087A1
公开(公告)日：2016-06-09
申请号：US14962648
申请日：2015-12-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yeongon CHO , Soojung RYU , Jeongae PARK , Woong SEO , Sangheon LEE , Seunghun JIN
CPC classification number: G06T15/005 , G06T1/60 , G06T7/50 , G06T11/40 , G06T15/80 , G06T17/20 , G06T2207/10024
Abstract: A tile-based rendering method includes performing binning of a current frame; generating an identification code of binning information or property information of a tile to be rendered in the current frame; comparing the identification code of the tile to be rendered to an identification code of a previous tile, wherein a location of the previous tile in a previous frame is the same as a location of the tile to be rendered in the current frame; and rendering the current frame by either re-using an image stored in a frame buffer or performing pixel processing of the tile to be rendered depending on a result of the comparing.
Abstract translation: 基于瓦片的呈现方法包括执行当前帧的合并; 生成要在当前帧中呈现的瓦片的合并信息或属性信息的识别码; 将要渲染的瓦片的识别码与先前瓦片的识别码进行比较，其中先前帧中的前一瓦片的位置与当前帧中要渲染的瓦片的位置相同; 以及通过重新使用存储在帧缓冲器中的图像或者根据比较的结果执行要渲染的图块的像素处理来渲染当前帧。
-
Patent Agency Ranking
16.发明申请PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF 审中-公开支持多模和多模支持方法的处理器公开(公告)号：US20150143081A1
公开(公告)日：2015-05-21
申请号：US14606240
申请日：2015-01-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU
CPC classification number: G06F15/8015 , G06F9/30058 , G06F9/3804 , G06F9/3851 , G06F9/3887 , G06F9/3889
Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.
Abstract translation: 实施例包括能够支持多模式和相应方法的处理器。 处理器包括前端单元，多个前端单元的多个处理元件; 以及控制器，被配置为确定是否由于条件分支而发生线程发散。 如果存在线程发散，则处理器可以设置控制信息以使用当前激活的前端单元来控制处理元件。 如果没有，则处理器可以使用当前激活的前端单元来设置控制信息以控制处理元件。
-
公开(公告)号：US20190155601A1
公开(公告)日：2019-05-23
申请号：US16256266
申请日：2019-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Moo-Kyoung CHUNG , Woong SEO , Ho-Young KIM , Soo-Jung RYU , Dong-Hoon YOO , Jin-Seok LEE , Yeon-Gon CHO , Chang-Moo KIM , Seung-Hun JIN
IPC: G06F9/30
Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.
-
公开(公告)号：US20170177491A1
公开(公告)日：2017-06-22
申请号：US15344267
申请日：2016-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woong SEO
IPC: G06F12/0895 , G06F12/0891
CPC classification number: G06F12/0895 , G06F12/0888 , G06F12/0891 , G06F2212/604 , Y02D10/13
Abstract: Provided is a processor including a plurality of devices. The processor includes a source processing device configured to identify data to request from another device, and a destination processing device configured to, in response to a request for the identified data from the source processing device using credit-based flow control, transmit the identified data to the source processing device using the credit-based flow control. The source processing device includes a credit buffer used for the credit-based flow control, the credit buffer being allocable to include a cache region configured to cache the transmitted identified data received by the source processing device.
-
公开(公告)号：US20160077969A1
公开(公告)日：2016-03-17
申请号：US14692828
申请日：2015-04-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woong SEO , Sangheon LEE , Soojung RYU , Yeongon CHO
IPC: G06F12/08
CPC classification number: G06F12/0802 , G06F12/0864 , G06F12/121 , G06F2212/1044 , G06F2212/604
Abstract: A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss being determined, determine, as an update candidate, a piece among pieces of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data.
Abstract translation: 高速缓冲存储器装置包括：标签比较器，被配置为比较由接收到的设定地址所指定的集合中包含的每个标签数据的高位，比较接收到的标签地址的高位， 标签数据与标签地址的其他位的片段，并且基于比较的结果来确定是否存在高速缓存命中或高速缓存未命中;以及更新控制器，被配置为响应于所确定的高速缓存未命中， 作为更新候选者，基于每个标签数据的高位和高位之间的比较结果，包括在集合中并与标签数据相对应的多条高速缓存数据中的一条 的标签地址，并用新数据更新更新候选。
-
公开(公告)号：US20160005191A1
公开(公告)日：2016-01-07
申请号：US14598590
申请日：2015-01-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seunghun JIN , Jeongae PARK , Woong SEO , Soojung RYU , Yeongon CHO
IPC: G06T11/00
CPC classification number: G06T11/001 , G06T15/04
Abstract: A method and corresponding apparatus are configured to generate a mipmap are configured to allocate a mipmap status register of a mipmap level generated with respect to a texture, receive a request for the texture, and calculate a mipmap level with respect to the texture. The method and corresponding apparatus are also configured to determine whether a mipmap of the calculated mipmap level exists using the mipmap status register and outputting a result indicative thereof, and determine whether to generate the mipmap of the mipmap level based on the result.
Abstract translation: 一种方法和相应的装置被配置为生成mipmap被配置为分配关于纹理生成的mipmap级别的mipmap状态寄存器，接收对纹理的请求，并且相对于纹理来计算mipmap级别。 所述方法和对应的装置还被配置为使用所述mipmap状态寄存器来确定所计算的mipmap级别的mipmap是否存在，并输出指示该mipmap状态寄存器的结果，并且基于该结果来确定是否生成mipmap级别的mipmap。
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.016 seconds)
