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    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF ERROR CORRECTION OF THE SAME
    11.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF ERROR CORRECTION OF THE SAME 审中-公开
    半导体存储器件，包括其的存储器系统及其错误校正方法

    公开(公告)号：US20160350181A1

    公开(公告)日：2016-12-01

    申请号：US15156804

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguhn CHA ,  Hoiju Chung ,  Uksong Kang ,  Chulwoo Park

    IPC: G06F11/10 ,  H03M13/15 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/02 ,  G11C29/42 ,  G11C29/52 ,  H03M13/1575

    Abstract: A semiconductor memory device capable of detecting a miscorrected bit generated in the semiconductor memory device outside the semiconductor memory device and a memory system including the semiconductor memory device are disclosed. The semiconductor memory device may generate first check bits based on first data received from the outside, divide an error correcting code (ECC) code word including the first data and the first check bits into a plurality of code word groups, and dispose a miscorrected bit, caused by error bits included in a first ECC code word group, in another ECC code word group rather than the first ECC code word group.

    Abstract translation: 公开了一种半导体存储器件，其能够检测在半导体存储器件外部的半导体存储器件中产生的错误校正位和包括该半导体存储器件的存储器系统。 半导体存储器件可以基于从外部接收的第一数据生成第一校验位，将包括第一数据和第一校验位的纠错码（ECC）码字分成多个码字组，并且配置未校正位 由包含在第一ECC码字组中的错误位引起的，在另一ECC码字组而不是第一ECC码字组中引起的。

    Semiconductor memory device with operation functions to be used during a modified read or write mode
    12.
    发明授权
    Semiconductor memory device with operation functions to be used during a modified read or write mode 有权
    具有操作功能的半导体存储器件在修改的读取/写入模式期间被使用

    公开(公告)号：US09292425B2

    公开(公告)日：2016-03-22

    申请号：US13966585

    申请日：2013-08-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyojin Choi ,  Chulwoo Park ,  Uksong Kang ,  Haksoo Yu

    IPC: G06F12/00 ,  G11C7/10 ,  G11C11/4076

    CPC classification number: G06F12/00 ,  G11C7/1006 ,  G11C11/4076

    Abstract: A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

    Abstract translation: 半导体存储器件执行修改的读取操作或修改的写入操作。 半导体存储器件包括存储单元阵列，读取电路和写入电路。 半导体存储器件还包括操作单元，根据通过地址线施加的操作分配信息，对由读取电路获得的读取数据执行操作，以减少进入修改的读取模式时的存储器访问时间。 此外，半导体存储器件可以可选地管理正常读取模式和修改读取模式，并且允许由操作单元输出的操作结果数据由修改读取模式下的写入电路写入。

    Semiconductor memory device managing flexible refresh skip area
    13.
    发明授权
    Semiconductor memory device managing flexible refresh skip area 有权

    公开(公告)号：US11631449B2

    公开(公告)日：2023-04-18

    申请号：US16389905

    申请日：2019-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uksong Kang ,  Hoiju Chung

    IPC: G11C11/40 ,  G11C11/406 ,  G11C11/408

    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

    SEMICONDUCTOR MEMORY DEVICE MANAGING FLEXIBLE REFRESH SKIP AREA
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE MANAGING FLEXIBLE REFRESH SKIP AREA 审中-公开

    公开(公告)号：US20190244657A1

    公开(公告)日：2019-08-08

    申请号：US16389905

    申请日：2019-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uksong Kang ,  Hoiju Chung

    IPC: G11C11/406 ,  G11C11/408

    CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/40626 ,  G11C11/4087

    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

    Semiconductor memory device managing flexible refresh skip area
    15.
    发明授权
    Semiconductor memory device managing flexible refresh skip area 有权

    公开(公告)号：US10311936B2

    公开(公告)日：2019-06-04

    申请号：US15233942

    申请日：2016-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uksong Kang ,  Hoiju Chung

    IPC: G11C11/406 ,  G11C11/408

    Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

    TIERED ECC SINGLE-CHIP AND DOUBLE-CHIP CHIPKILL SCHEME
    17.
    发明申请
    TIERED ECC SINGLE-CHIP AND DOUBLE-CHIP CHIPKILL SCHEME 有权
    独特的ECC单芯片和双芯片芯片方案

    公开(公告)号：US20160011940A1

    公开(公告)日：2016-01-14

    申请号：US14606334

    申请日：2015-01-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong Hu ,  Uksong Kang ,  Hongzhong Zheng

    IPC: G06F11/10

    CPC classification number: G06F11/1044 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1048 ,  G06F11/106 ,  G06F11/108 ,  G06F2211/1057

    Abstract: Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system, comprising: a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

    Abstract translation: 示例性实施例提供了一种分层纠错码（ECC）Chipkill系统，包括：整合到多个存储器装置的至少一部分中的装置ECC，其校正相应存储装置中的n位存储装置级故障，并发送 当任何存储器件级故障大于n位且超出器件ECC器件的校正能力时，存储器件故障信号; 并且多个存储器设备外部的系统级ECC设备响应于基于系统ECC奇偶校验接收存储器件故障信号以校正存储器件故障。

    Semiconductor memory device, memory system including the same, and method of error correction of the same
    20.
    发明授权
    Semiconductor memory device, memory system including the same, and method of error correction of the same 有权

    公开(公告)号：US10140176B2

    公开(公告)日：2018-11-27

    申请号：US15156804

    申请日：2016-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanguhn Cha ,  Hoiju Chung ,  Uksong Kang ,  Chulwoo Park

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  G11C29/02 ,  G11C29/42

    Abstract: An error correcting method of a semiconductor memory device includes receiving first data from outside the semiconductor memory device. First check bits are generated based on the first data and a first parity generator matrix. The first parity generator matrix includes a plurality of columns of bits. The plurality of columns of bits are arranged in a plurality of parity generator matrix groups. An error correcting code (ECC) code word including a plurality of ECC code word groups is stored in the plurality of memory cell groups. Each of the plurality of ECC code word groups have the first data and the first check bits. The plurality of ECC code word groups correspond to the plurality of parity generator matrix groups, respectively. For each parity generator matrix group of the first parity generator matrix, a result value of a bit-by-bit exclusive OR (XOR) operation performed on any two columns included in the parity generator matrix group is equal to a column number of a column that is not included in the parity generator matrix group. Thus, when a first ECC code word group, from among the plurality of ECC code word groups, includes error bits, a miscorrected bit that would be caused by the error bits as a result of performing an error correction operation on the first ECC code word group is located in an ECC code word group other than the first ECC code word group.

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