公开(公告)号：US20240038292A1

公开(公告)日：2024-02-01

申请号：US18357204

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/40622

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

公开(公告)号：US20230418487A1

公开(公告)日：2023-12-28

申请号：US18136915

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongcheol Kim ,  Kiheung Kim ,  Taeyoung Oh ,  Kyungho Lee

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.

公开(公告)号：US20230342050A1

公开(公告)日：2023-10-26

申请号：US18304813

申请日：2023-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Taeyoung Oh ,  Hoseok Seol

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0611 ,  G06F3/0673

Abstract: Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.

公开(公告)号：US10242719B2

公开(公告)日：2019-03-26

申请号：US15416140

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G06F1/00 ,  G11C5/14 ,  G06F1/26 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US12175099B2

公开(公告)日：2024-12-24

申请号：US18302276

申请日：2023-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

公开(公告)号：US20240404584A1

公开(公告)日：2024-12-05

申请号：US18678401

申请日：2024-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyung-Ho Lee ,  Hyongryol Hwang

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

Abstract: An example memory device includes a memory cell array, a row hammer management circuit, and a read-modify-write (RMW) driver. The memory cell array includes a plurality of memory cell rows and stores count data for a number of accesses to each memory cell row. The row hammer management circuit performs an RMW operation that reads out count data corresponding to a target memory cell row among the memory cell rows, updates the read-out count data, and writes the updated count data in the memory cell array. The RMW driver generates control signals to control the RMW operation based on a precharge command. The target memory cell row is precharged after a predetermined time is elapsed from a time point where the precharge command is applied.

公开(公告)号：US12080334B2

公开(公告)日：2024-09-03

申请号：US17885081

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyoung Oh

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C11/4096

Abstract: A semiconductor memory device includes a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access on each memory cell row to store the counted values in count cells of each memory cell row as count data. A hammer address queue in the row hammer management circuit stores candidate hammer addresses, which are intensively accessed, in response to a number of the candidate hammer addresses reaching a second number, transitions a logic level of an error signal provided to the memory controller, and, in response to the number of the candidate hammer addresses reaching the first number, outputs one of the candidate hammer addresses as a hammer address. The refresh control circuit performs a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US11621034B2

公开(公告)日：2023-04-04

申请号：US17376915

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10699770B2

公开(公告)日：2020-06-30

申请号：US16579994

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10460793B2

公开(公告)日：2019-10-29

申请号：US16278339

申请日：2019-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C8/18 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.