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    TRANSMITTING DEVICES THAT PROVIDE TRANMISSION SIGNALS HAVING ENLARGED DATA EYES
    12.
    发明申请
    TRANSMITTING DEVICES THAT PROVIDE TRANMISSION SIGNALS HAVING ENLARGED DATA EYES 有权

    公开(公告)号：US20250071009A1

    公开(公告)日：2025-02-27

    申请号：US18945640

    申请日：2024-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seongyeal Yang ,  Moonchul Choi ,  Sungyong Cho ,  Jaehyeok Baek

    IPC: H04L27/36

    Abstract: Provided is a transmitting device for enlarging the size of a data eye of a transmission signal. The transmitting device includes an output driver including a plurality of driver circuits that drive a plurality of multi-level signals onto an output node, and a logic circuit configured to detect a direction of a pull-up or pull-down operation of each of the plurality of driver circuits by transitions of the plurality of driver control signals and generate pulse signals. The plurality of multi-level signals are driven based on a plurality of driver control signals and pulse signals, respectively, and the logic circuit provides a pulse signal to at least one static driver circuit connected to a driver control signal that does not transition, from among the plurality of driver circuits.

    Memory systems and controllers for generating a command address and methods of operating same
    13.
    发明授权
    Memory systems and controllers for generating a command address and methods of operating same 有权

    公开(公告)号：US12235757B2

    公开(公告)日：2025-02-25

    申请号：US18318906

    申请日：2023-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae Kim ,  Sungyong Cho ,  Minho Maeing ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

    IPC: G06F11/10 ,  G06F12/06

    Abstract: A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.

    ZQ CALIBRATION CIRCUIT, OPERATION METHOD OF THE ZQ CALIBRATION CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE
    14.
    发明公开
    ZQ CALIBRATION CIRCUIT, OPERATION METHOD OF THE ZQ CALIBRATION CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240127871A1

    公开(公告)日：2024-04-18

    申请号：US18235848

    申请日：2023-08-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Donggun An ,  Jaehyeok Baek ,  Sungyong Cho ,  Moonchul Choi

    IPC: G11C7/10

    CPC classification number: G11C7/1048 ,  G11C2207/2254

    Abstract: A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.

    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION
    15.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHODS OF OPERATION 审中-公开

    公开(公告)号：US20230185460A1

    公开(公告)日：2023-06-15

    申请号：US18076628

    申请日：2022-12-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheung Kim ,  Taeyoung Oh ,  Hyeran Kim ,  Sungyong Cho ,  Kyungsoo Ha

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.

    Cleaning method and cleaning system for reticle pod
    16.
    发明授权
    Cleaning method and cleaning system for reticle pod 有权

    公开(公告)号：US11143974B1

    公开(公告)日：2021-10-12

    申请号：US17021120

    申请日：2020-09-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongseung Moon ,  Sungyong Cho

    IPC: G03F7/20 ,  G03F1/66 ,  H01L21/673

    Abstract: A method of cleaning a reticle pod and an exposure method, the method of cleaning the reticle pod including receiving the reticle pod that includes an inner pod and an outer pod surrounding the inner pod; disassembling the inner pod from the outer pod; inspecting a surface of a base plate of the inner pod to detect defects; performing a local plasma cleaning process at a defect location on the surface of the base plate; performing a wet cleaning process on the inner pod; and reassembling the inner pod to the outer pod.

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